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1/176 november 2002 m psd323x flash programmable system devices with 8032 microcontroller core and 64kbit sram features summary n the m psd323x devices combine a flash psd architecture with an 8032 microcontroller core. the m psd323x devices of flash psds feature dual banks of flash memory, sram, general purpose i/o and programmable logic, supervi- sory functions and access via usb, i 2 c, adc, ddc and pwm channels, and an on-board 8032 microcontroller core, with two uarts, three 16-bit timer/counters and two external interrupts. as with other flash psd families, the m psd323x devices are also in-system pro- grammable (isp) via a jtag isp interface. n large 8kbyte sram with battery back-up option n dual bank flash memories 128kbyte or 256kbyte main flash memory 32kbyte secondary flash memory n content security block access to flash memory n programmable decode pld for flexible address mapping of all memories within 8032 space. n high-speed clock standard 8032 core (12-cycle) n usb interface (some devices only) n i 2 c interface for peripheral connections n 5 pulse width modulator (pwm) channels n analog-to-digital converter (adc) n standalone display data channel (ddc) n six i/o ports with up to 50 i/o pins n 3000 gate pld with 16 macrocells n supervisor functions with watchdog timer n in-system programming (isp) via jtag n zero-power technology n single supply voltage 4.5 to 5.5v 3.0 to 3.6v figure 1. 52-lead, thin, quad, flat package figure 2. 80-lead, thin, quad, flat package tqfp52 (t) tqfp80 (u)
m psd323x 2/176 table of contents summary description . . . . . . . . ........................................... .......11 m psd323x devices product matrix (table 1.) . . . . . ............................... ....12 tqfp52 connections (figure 3.) . . . . . . . . . . . . . .....................................12 tqfp80 connections (figure 4.) . . . . . . . . . . . . . .....................................13 80-pin package pin description (table 2.) ...........................................14 52 pin package i/o port . . . . . . . . . . . . . . . . . . . . ....................................16 architecture overview . . . . . . . . . . . . . . . . . . . ....................................17 memory organization . . . . . . . . . . . . . ..............................................17 memory map and address space (figure 5.) . . . . . ............................. .......17 registers . ............................. .......................................17 8032 mcu registers (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 configuration of ba 16-bit registers (figure 7.) . . . ....................................18 stack pointer (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................18 psw (program status word) register (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....19 data memory . . ......................... .......................................19 ram................................................... ......................19 interrupt location of program memory (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 xram-ddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 xram-psd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................19 sfr.........................................................................20 ram address (table 3.) . . . . . . . . . . . . . . . . . . . . .....................................20 addressing modes. . . . . . . . . . . . . . . . . . . ...........................................20 direct addressing (figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........20 indirect addressing (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 indexed addressing (figure 13.) . . . . . ..............................................21 arithmetic instructions . . .........................................................21 arithmetic instructions (table 4.). . . . . ..............................................22 logical instructions . . . . .........................................................22 logical instructions (table 5.) . . . . . . . . . . ...........................................23 data transfers. ......................... ................................ .......24 data transfer instructions that access internal data memory space (table 6.) . . . ...........24 shifting a bcd number two digits to the right (using direct movs: 14 bytes) (table 7.) . . . ....25 shifting a bcd number two digits to the right (using direct xchs: 9 bytes) (table 8.) . . . . . . . . 25 shifting a bcd number one digit to the right (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....25 data transfer instruction that access external data memory space (table 10.) ..............26 lookup table read instruction (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............26 boolean instructions . . . . . . . . . . ..................................................27 boolean instructions (table 12.) . . . . . . . . . . . . . . . . . . .................................27 relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....27
3/176 m psd323x jump instructions . . . . . . . . . . . . . . . . . . . ...........................................28 unconditional jump instructions (table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 machine cycles ................................................................29 conditional jump instructions . . . ..................................................29 state sequence in m psd323x devices (figure 14.) . . . . . . ..............................30 m psd3200 hardware description . . . . . . . . . . .....................................31 m psd323x devices functional modules (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 mcu module discription . . . . . . . . . ..............................................32 special function registers . . . . . ........................................... .......32 sfr memory map (table 15.) .....................................................32 list of all sfr (table 16.) . . . . . . . . . . ..............................................33 psd module register address offset (table 17.). . . . . . . . . . . . . . . . . . . . . . . . ..............37 interrupt system. . . . . . . . . . . . ..................................................39 external int0 . . . . . . . . . . . . . . . . . . . . . . . ...........................................39 timer 0 and 1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................39 timer 2 interrupt . ..............................................................39 i2c interrupt ...................................................................39 external int1 . . . . . . . . . . . . . . . . . . . . . . . ...........................................39 ddc interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........39 usb interrupt ....................................................... ...........39 usart interrupt . ..............................................................40 interrupt system (figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 sfr register (table 18.). . . . . . . ..................................................41 interrupt priority structure . . . . . . . . . . . . . . . . . . . . ....................................41 interrupts enable structure . . . . . . . . . . . . . . . . . . . ....................................41 priority levels (table 19.) . . . . . . . . . . . . . . . . . . . . ....................................41 description of the ie bits (table 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 description of the iea bits (table 21.) . . . . . . . ................................ .......42 description of the ip bits (table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 description of the ipa bits (table 23.) . . . . . . . ................................ .......42 how interrupts are handled ......................... ..............................43 vector addresses (table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........43 power-saving mode. . . . . . ......................................................44 idle mode. . . . . . . . . . . . . . . . . . . . . . . ..............................................44 power-down mode . . . . . . . . . . . ........................................... .......44 power-saving mode power consumption (table 25.) . . . . . . . . . . . . . . . . . . . . ..............44 power control register . .........................................................44 pin status during idle and power-down mode (table 26.) . . . . . . . . . . . . . . . . . ..............44 description of the pcon bits (table 27.) . . . . . . . .....................................44 idle mode. . . . . . . . . . . . . . . . . . . . . . . ..............................................44
m psd323x 4/176 i/o ports (mcu module) ..........................................................46 i/o port functions (table 28.) . . . . . . . . . . ...........................................46 p1sfs (91h) (table 29.). . . . . . . ..................................................46 p3sfs (93h) (table 30.). . . . . . . ..................................................46 p4sfs (94h) (table 31.). . . . . . . ..................................................46 port type and description . . . . ........................................... .......47 port type and description (part 1) (figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........47 port type and description (part 2) (figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........48 oscillator . ............................................................... ....49 oscillator (figure 19.) . . . . . . . . . . . . . . . . ...........................................49 supervisory . . . . . ..............................................................49 reset configuration (figure 20.). . . . . . . . . . . ................................ .......49 external reset . ......................... .......................................50 low vdd voltage reset . . . . . . . . . . . . . . . . . . . . . . . . .................................50 watchdog timer overflow . . . . . . ........................................... .......50 usbreset....................................................................50 watchdog timer . . . . . . . . . . . . . . . . . . . . ...........................................51 watchdog timer key register (wdkey: 0aeh) (table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . ....51 description of the wdkey bits (table 33.) . . . . . . . . ...................................51 reset pulse width (figure 21.). . . . . . . . ...........................................52 watchdog timer clear register (wdrst: 0a6h) (table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 description of the wdrst bits (table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............52 timer/counters (timer0, timer1 and timer2) ............................. .......53 timer0 and timer1 . . . . . . . . . . . ..................................................53 control register (tcon) (table 36.). . . . . . . . . . . .....................................53 description of the tcon bits (table 37.) . . . . . . . . . . . . . . ..............................53 tmod register (tmod) (table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 description of the tmod bits (table 39.) ............................................54 timer/counter mode 0: 13-bit counter (figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 timer/counter mode 2: 8-bit auto-reload (figure 23.) . . . . . . . . . . . . . . . . . . . . ..............55 timer/counter mode 3: two 8-bit counters (figure 24.). ......................... .......56 timer 2 . . . . . .................................................................56 timer/counter 2 control register (t2con) (table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....57 description of the t2con bits (table 41.) ...........................................57 timer/counter2 operating modes (table 42.). . . . . . . . . . . ..............................58 timer 2 in capture mode (figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 timer 2 in auto-reload mode (figure 26.) . . . . . . . ....................................59
5/176 m psd323x standard serial interface (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 multiprocessor communications . ..................................................60 serial port control register. ......................................................60 serial port control register (scon) (table 43.). . . ....................................60 description of the scon bits (table 44.) . . . . . . . .....................................61 timer 1-generated commonly used baud rates (table 45.) . . . . . . . . . . . . . . ..............62 serial port mode 0, block diagram (figure 27.) . . . . . . . . . . . . . . . . . . . . . ..................65 serial port mode 0, waveforms (figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 serial port mode 1, block diagram (figure 29.) . . . . . . . . . . . . . . . . . . . . . ..................66 serial port mode 1, waveforms (figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 serial port mode 2, block diagram (figure 31.) . . . . . . . . . . . . . . . . . . . . . ..................67 serial port mode 2, waveforms (figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 serial port mode 3, block diagram (figure 33.) . . . . . . . . . . . . . . . . . . . . . ..................68 serial port mode 3, waveforms (figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 analog-to-digital convertor (adc) ...........................................70 adc interrupt. . ......................... .......................................70 a/d block diagram (figure 35.). . . . . . . . . . . . . . . . ....................................70 adc sfr memory map (table 46.) . . ..............................................71 description of the acon bits (table 47.) . . . . . . . .....................................71 adc clock input (table 48.) . . . . ..................................................71 pulse width modulation (pwm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4-channel pwm unit (pwm 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 four-channel 8-bit pwm block diagram (figure 36.) ..... ..............................73 pwm sfr memory map (table 49.) . . . . . . . . . . . .....................................74 programmable period 8-bit pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 programmable pwm 4 channel block diagram (figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 pwm 4 channel operation . . . . . . . . . . . . ...........................................76 pwm 4 with programmable pulse width and frequency (figure 38.) . . . . . . . . . . . . . . . . . .....76 i2c interface . . ......................... ................................ .......77 block diagram of the i2c bus serial i/o (figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . ...........77 serial control register (sxcon: s1con, s2con) (table 50.) . . . . . . . . . . . . . . . . . . . . .......78 description of the sxcon bits (table 51.) ...........................................78 selection of the serial clock frequency scl in master mode (table 52.) . . . . . . . . . . . . . . . ....78 serial status register (sxsta: s1sta, s2sta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 data shift register (sxdat: s1dat, s2dat) . . . . . . . . . . . . . . . . . . . . . . . . . . ..............79 serial status register (sxsta) (table 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........79 description of the sxsta bits (table 54.) . ...........................................79 data shift register (sxdat: s1dat, s2dat) (table 55.) . ..............................79 address register (sxadr: s1adr, s2adr) . . . . . ....................................80 address register (sxadr) (table 56.) . . . ...........................................80 start /stop hold time detection register (s1setup, s2setup) (table 57.) . . . . . . . . . . . . . . . . 80 system cock of 40mhz (table 58.). . . . . . . . . . . . . . . . .................................80 system clock setup examples (table 59.) . . . . ................................ .......80 programmer's guide for i2c and ddc2 . ............................................81
m psd323x 6/176 ddc interface . ......................... .......................................83 ddc interface block diagram (figure 40.) ...........................................83 special function register for the ddc interface. . . . . . . . . . . . . . . . . . . . . ..................84 ddc sfr memory map (table 60.) . . . . . . . . . . . . . ...................................84 description of the ddcon register bits (table 61.). . . . . . . . . . . . . .......................85 swneb bit function (table 62.) . ........................................... .......86 host type detection . . . . . . . . . . ........................................... .......87 host type detection (figure 41.) . . . . . . . . . . . . . .....................................87 ddc1 protocol. ......................... .......................................88 transmission protocol in the ddc1 interface (figure 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ddc2b protocol . . . . . . . . .......................................................89 conceptual structure of the ddc interface (figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....89 usb hardware . . . . . . . . . . . . . . . . . . . ..............................................90 usb related registers . . . . . . . . . ..................................................90 usb address register (uadr: 0eeh) (table 63.) . . . . .................................90 description of the uadr bits (table 64.) . . . . . . . . . . . . . . ..............................90 usb interrupt enable register (uien: 0e9h) (table 65.) . . . . . . . . . . . . . . . . . . . . . ...........91 description of the uien bits (table 66.) . . . . . . . . . . . . . . . ..............................91 usb interrupt status register (uista: 0e8h) (table 67.) . . . . . . . . . ......................91 description of the uista bits (table 68.) . . . . . . . . . . . . . . ..............................92 usb endpoint0 transmit control register (ucon0: 0eah) (table 69.) ................. ....93 description of the ucon0 bits (table 70.) . . . . . . . ....................................93 usb endpoint1 (and 2) transmit control register (ucon1: 0ebh) (table 71.). . . . . . . . . . .....94 description of the ucon1 bits (table 72.) . . . . . . . ....................................94 usb control register (ucon2: 0ech) (table 73.). ............................. .......95 description of the ucon2 bits (table 74.) . . . . . . . ....................................95 usb endpoint0 status register (usta: 0edh) (table 75.) . . . . . . . . . . . . . . . . . . . ...........95 description of the usta bits (table 76.). . ...........................................95 usb endpoint0 data receive register (udr0: 0efh) (table 77.). . . . . . . . . . . . . . . . . . . . . ....95 usb endpoint0 data transmit register (udt0: 0e7h) (table 78.) . .......................95 usb endpoint1 data transmit register (udt1: 0e6h) (table 79.) . .......................95 usb sfr memory map (table 80.). . . . . . . . . . . . .....................................96 transceiver . . . . . . . . . . . . . . . . . ........................................... .......97 low speed driver signal waveforms (figure 44.) . . . . .................................97 receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................98 differential input sensitivity over entire common mode range (figure 45.) . . . . . . . . . . .......98 external usb pull-up resistor . . ..................................................99 usb data signal timing and voltage levels (figure 46.). . . . . . . . . . . . . . . . . . . . . ...........99 receiver jitter tolerance (figure 47.). . . . . . . . . . . . . . . . . ..............................99 differential to eop transition skew and eop width (figure 48.). . . . . . . . . . . . . . . ..........100 differential data jitter (figure 49.) . . . . . . . . . . . . . ...................................100 transceiver dc characteristics (table 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........101 transceiver ac characteristics (table 82.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7/176 m psd323x psd module . . . . . . .............................................................102 functional overview . . . . . . . . . . . . . . . . . . . . . . . . ............................. ......102 psd module block diagram (figure 50.). . . . . . . ............................. ......103 in-system programming (isp) .............................................. ......104 methods of programming different functional blocks of the psd module (table 83.) . . . . . . . 104 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................105 psdsoft express development tool (figure 51.) . ....................................105 psd module register description and address offset . ......................106 register address offset (table 84.) . . . . . . . . . ................................ ......106 psd module detailed operation . .............................................107 memory blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................................107 primary flash memory and secondary flash memory description. . . . . . . . . . . . . . . . . . . . . ...107 memory block select signals . . . .................................................107 instructions . . . . . . . . . . . . . . . . . . . . . .............................................108 instructions (table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................109 power-down instruction and power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........110 read. . . . . . . . . . . . . . . . . . . . . . . . . . .............................................110 status bit (table 86.). . . . . ......................................................111 programming flash memory . . . . . . . . . . . . . . . . . ....................................112 data polling flowchart (figure 52.) . . . . . ...........................................112 data toggle flowchart (figure 53.). . . . . . . . . . . . . . . . . . . .............................113 erasing flash memory. . . . . . . . . . . . . .............................................114 specific features. . . . . . . . . . . . . . . . . .............................................115 sector protection/security bit definition flash protection register (table 87.) . . . ..........115 sector protection/security bit definition secondary flash protection register (table 88.) . . . . 115 sram . . . . . . ................................................................116 sector select and sram select . . . . . . . . . . . . . . . . . . . . . .............................116 priority level of memory and i/o components in the psd module (figure 54.) . . . . . . . . ....117 vm register (table 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 separate space mode (figure 55.) . . . . . . . . . . . . . . . . ................................118 combined space mode (figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........119 page register (figure 57.) . . . . . .................................................119 plds ..........................................................................120 dpld and cpld inputs (table 90.) . . .............................................120 the turbo bit in psd module . . . . . . . . . . . . . . ....................................120 pld diagram (figure 58.) . . . . . . . . . . . . . . . . . . . . ...................................121 decode pld (dpld) . . . . . . .....................................................122 dpld logic array (figure 59.) . . .................................................122 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . ...................................123 macrocell and i/o port (figure 60.) . . . . . . . . . . . . ....................................123 output macrocell port and data bit assignments (table 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
m psd323x 8/176 product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . ................................125 cpld output macrocell (figure 61.) . . . . . . . . . . . . . . . . . . . . . . . . . ......................125 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 input macrocell (figure 62.). . . . . . . . . . . . . . . . . . . . . . . . . .............................126 i/o ports (psd module) . . . . . . . .................................................127 general port architecture . . . . . . . . . . . . . . . . . . . . ...................................127 general i/o port architecture (figure 63.). ..........................................127 port operating modes . . . . . . . . . ........................................... ......128 mcu i/o mode. ......................... ......................................128 pld i/o mode . ...............................................................128 address out mode. . . . . . . . . . . . ........................................... ......128 peripheral i/o mode . . . . . . . . . . . . . . . . . . . . . . . . ...................................128 jtag in-system programming (isp) . . . . . . . . . . . . ..................................128 peripheral i/o mode (figure 64.). .................................................129 port operating modes (table 92.) . . . . . . . . . . . ................................ ......129 port operating mode settings (table 93.). . . . . . . . ............................. ......129 i/o port latched address output assignments (table 94.) . . . . . . . . . . . . . . . . . . . . . . . ......129 port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................130 port configuration registers (pcr) (table 95.) . . . . . . . . . . . . . . . . . . . . . . . . . .............130 port pin direction control, output enable p.t. not defined (table 96.) . . . . . . . .............130 port pin direction control, output enable p.t. defined (table 97.) . . . . . . . . . . . . . . . . . . . . . . . 130 port direction assignment example (table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . .............130 port data registers . . . .........................................................131 drive register pin assignment (table 99.) . . . . . . . . ............................... ...131 ports a and b functionality and structure . . . . . . ...................................132 port a and port b structure (figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...132 port c functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................133 port c structure (figure 66.) . . . . . . . . . . . . . . . . . . . . . ................................133 port d functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................134 port d structure (figure 67.) . . . . . . . . . . . . . . . . . . . . . ................................134 external chip select . . . . . . . . . . . . . . . . . . . . . . . . ...................................135 port d external chip select signals (figure 68.) . ....................................135 power management . . . . . . . . . .................................................136 apd unit (figure 69.) . . . . . . . . . .................................................136 enable power-down flow chart (figure 70.) . . . . . . ..................................137 power-down mode's effect on ports (table 101.). . . . . . . . . . . . . . . . . . . . . . . . . . . ..........137 pld power management . . . . . . . . . . . . . . . . . . . . . ..................................138 psd chip select input (csi, pd2) . . . .............................................138 input clock. . . . . . . . . . . . . . .....................................................138 input control signals . . . . . ......................................................138 power management mode registers pmmr01 (table 102.) . . . . .................. ......138 power management mode registers pmmr21 (table 103.) . . . . .................. ......139 apd counter operation (table 104.) . . . . ..........................................139
9/176 m psd323x reset timing and device status at reset . . . . . . . . .............................140 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................... ...140 i/o pin, register and pld status at reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 reset of flash memory erase and program cycles . . . . . . . . . . . . . . .....................140 reset (reset) timing (figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................140 status during power-on reset, warm reset and power-down mode (table 105.). . . . . . . . . 141 programming in-circuit using the jtag serial interface . . . . . . . . . . . . . . . . . . ...142 standard jtag signals. ........................................................142 jtag port signals (table 106.). . .................................................142 jtag extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...142 security and flash memory protection . . . . . . . ......................................142 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........142 ac/dc parameters . . . . . . ......................................................143 pld icc /frequency consumption (5v range) (figure 72.) . . . . . .................. ......143 pld icc /frequency consumption (3v range) (figure 73.) . . . . . .................. ......143 psd module example, typ. power calculation at v cc = 5.0v (turbo mode off) (table 107.). 144 maximum rating. . . . . . . . . . . . . . . . . . . . . ..........................................145 absolute maximum ratings (table 108.) . . . . . . . . . . . . . . .............................145 dc and ac parameters. . . . . . . ........................................... ......146 operating conditions (5v devices) (table 109.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...146 operating conditions (3v devices) (table 110.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...146 ac symbols for timing (table 111.) . . . . . . . . . . . . . . . . . . . . . . . . . ......................147 switching waveforms key (figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 dc characteristics (5v devices) (table 112.). . . . ....................................148 dc characteristics (3v devices) (table 113.). . . . ....................................150 external program memory read cycle (figure 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 external program memory ac characteristics (with the 5v mcu module) (table 114.) . . . . . . . 152 external program memory ac characteristics (with the 3v mcu module) (table 115.) . . . . . . . 153 external clock drive (with the 5v mcu module) (table 116.) . . . . . . . . . . . . . . . . . . . . . . . . ...153 external clock drive (with the 3v mcu module) (table 117.) . . . . . . . . . . . . . . . . . . . . . . . . ...153 external data memory read cycle (figure 76.) . . . . . ................................154 external data memory write cycle (figure 77.). . . . . . . . . . . . . . . . . . . . . . . . . . . ..........154 external data memory ac characteristics (with the 5v mcu module) (table 118.). ..........155 external data memory ac characteristics (with the 3v mcu module) (table 119.). ..........156 a/d analog specification (table 120.). . . . . . . . . . . . . . . . . .............................156 input to output disable / enable (figure 78.) . . . . . ...................................157 cpld combinatorial timing (5v devices) (table 121.) . ......................... ......157 cpld combinatorial timing (3v devices) (table 122.) . ......................... ......157 synchronous clock mode timing pld (figure 79.) . . . . . . . . . . . . ......................158 cpld macrocell synchronous clock mode timing (5v devices) (table 123.) ...............158 cpld macrocell synchronous clock mode timing (3v devices) (table 124.) ...............159 asynchronous reset / preset (figure 80.) . . . . . . ...................................160
m psd323x 10/176 asynchronous clock mode timing (product term clock) (figure 81.) . . . . . . . . . .............160 cpld macrocell asynchronous clock mode timing (5v devices) (table 125.) . . . . . . . . . . . . . . 160 cpld macrocell asynchronous clock mode timing (3v devices) (table 126.) . . . . . . . . . . . . . . 161 input macrocell timing (product term clock) (figure 82.) . . . . . . . . . ......................162 input macrocell timing (5v devices) (table 127.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 input macrocell timing (3v devices) (table 128.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 program, write and erase times (5v devices) (table 129.) . . .........................163 program, write and erase times (3v devices) (table 130.) . . .........................163 peripheral i/o read timing (figure 83.) ...........................................164 port a peripheral data mode read timing (5v devices) (table 131.) . . . . . . . . . . . . . . . . . . . . 164 port a peripheral data mode read timing (3v devices) (table 132.) . . . . . . . . . . . . . . . . . . . . 164 peripheral i/o write timing (figure 84.) ..........................................165 port a peripheral data mode write timing (5v devices) (table 133.) . . . . . . . . . ..........165 port a peripheral data mode write timing (3v devices) (table 134.) . . . . . . . . . ..........165 reset (reset) timing (figure 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................166 reset (reset) timing (5v devices) (table 135.) . . . . ................................166 reset (reset) timing (3v devices) (table 136.) . . . . ................................166 v stbyon definitions timing (5v devices) (table 137.) .... .............................166 v stbyon timing (3v devices) (table 138.). . . . . . . ...................................166 isc timing (figure 86.) . ........................................................167 isc timing (5v devices) (table 139.) .......... ....................................167 isc timing (3v devices) (table 140.) .......... ....................................168 mcu module ac measurement i/o waveform (figure 87.) . . . . . . . . . . . . . . . . . . . ..........168 psd module ac float i/o waveform (figure 88.) . . . ................................168 external clock cycle (figure 89.) . . . . . . . . . . . . . . . . . ................................169 recommended oscillator circuits (figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........169 psd module ac measurement i/o waveform (figure 91.) . . . . . . . .....................169 psd moduleac measurement load circuit (figure 92.) . . . . . . . . . . . . . . . . . . . . ..........169 capacitance (table 141.) . . . . . . . . . . . . . . . . . . . . ...................................169 part numbering . . . . . . . . . .....................................................174 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........170 part numbering . . . . . . . . . .....................................................174
11/176 m psd323x summary description n dual bank flash memories concurrent operation, read from memory while erasing and writing the other. in-appli- cation programming (iap) for remote updates large 128kbyte or 256kbyte main flash memory for application code, operating sys- tems, or bit maps for graphic user interfaces large 32kbyte secondary flash memory di- vided in small sectors. eliminate external ee- prom with software eeprom emulation secondary flash memory is large enough for sophisticated communication protocol (usb) during iap while continuing critical system tasks n large sram with battery back-up option 8kbyte sram for rtos, high-level languag- es, communication buffers, and stacks n programmable decode pld for flexible address mapping of all memories place individual flash and sram sectors on any address boundary built-in page register breaks restrictive 8032 limit of 64kbyte address space special register swaps flash memory seg- ments between 8032 aprogramo space and adatao space for efficient in-application pro- gramming n high-speed clock standard 8032 core (12-cycle) 40mhz operation at 5v, 24mhz at 3.3v 2 uarts with independent baud rate, three 16-bit timer/counters and two external inter- rupts n usb interface ( m psd3234a-40 only) supports usb 1.1 slow mode (1.5mbit/s) control endpoint 0 and interrupt endpoints 1 and 2 n i 2 c interface for peripheral connections capable of master or slave operation n 5 pulse width modulator (pwm) channels four 8-bit pwm units one 8-bit pwm unit with programmable peri- od n 4-channel, 8-bit analog-to-digital converter (adc) with analog supply voltage (v ref ) n standalone display data channel (ddc) for use in monitor, projector, and tv applica- tions compliant with vesa standards ddc1 and ddc2b eliminate external ddc prom n six i/o ports with up to 50 i/o pins multifunction i/o: gpio, ddc, i 2 c, pwm, pld i/o, supervisor, and jtag eliminates need for external latches and logic n 3000 gate pld with 16 macrocells create glue logic, state machines, delays, etc. eliminate external pals, plds, and 74hcxx simple psdsoft express software ...free n supervisor functions generates reset upon low voltage or watch- dog time-out. eliminate external supervisor device reset input pin; reset output via pld n in-system programming (isp) via jtag program entire chip in 10 - 25 seconds with no involvement of 8032 allows efficient manufacturing, easy product testing, and just-in-time inventory eliminate sockets and pre-programmed parts program with flashlink tm cable and any pc n content security programmable security bit blocks access of device programmers and readers n zero-power technology memories and pld automatically reach standby current between input changes n packages 52-pin tqfp 80-pin tqfp: allows access to 8032 address/ data/control signals for connecting to external peripherals
m psd323x 12/176 table 1. m psd323x devices product matrix figure 3. tqfp52 connections note: 1. pull-up resistor required on pin 5 (2k w for 3v devices, 7.5k w for 5v devices) for all 52-pin devices, with or without usb function. part no. main flash (bit) sec. flash (bit) sram (bit) macro -cells i/o pins pwm ch. timer / ctr uart ch. i 2 c adc ch. ddc usb v cc mhz pins upsd 3234 a-40 2m 256k 64k 16 41 or 50 5 3 2 1 4 yes yes 5v 40 52 or 80 upsd 3234 bv-24 2m 256k 64k 16 50 5 3 2 1 4 yes 3v 24 80 upsd 3233 b-40 1m 256k 64k 16 41 or 50 5 3 2 1 4 yes 5v 40 52 or 80 upsd 3233 bv-24 1m 256k 64k 16 41 or 50 5 3 2 1 4 yes 3v 24 52 or 80 39 p1.5 / adc1 38 p1.4 / adc0 37 p1.3 / txd1 36 p1.2 / rxd1 35 p1.1 / t2x 34 p1.0 / t2 33 v cc 32 xtal2 31 xtal1 30 p3.7 / scl1 29 p3.6 / sda1 28 p3.5 / t1 27 p3.4 / t0 pd1 pc7 pc6 pc5 usb pc4 usb+ v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 (1) 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 vref gnd reset pb6 pb7 adc3 adc2 14 15 16 17 18 19 20 21 22 23 24 25 26 p4.7 / pwm4 p4.6 / pwm3 p4.5 / pwm2 p4.4 / pwm1 p4.3 / pwm0 gnd p4.2 / ddc vsync p4.1 / ddc scl p4.0 / ddc sda p3.0 / rxd p3.1 / txd p3.2 / exint0 p3.3 / exint1 ai05790c
13/176 m psd323x figure 4. tqfp80 connections note: nc = not connected 1. pull-up resistor required on pin 8 (2k w for 3v devices, 7.5k w for 5v devices) for all 82-pin devices, with or without usb function. 60 p1.5 / adc1 59 p1.4 / adc0 58 p1.3 / txd1 57 p2.3, a11 56 p1.2 / rxd1 55 p2.2, a10 54 p1.1 / t2x 53 p2.1, a9 52 p1.0 / t2 51 p2.0, a8 50 v cc 49 xtal2 48 xtal1 47 p0.7, ad7 46 p3.7 / scl1 45 p0.6, ad6 44 p3.6 / sda1 43 p0.5, ad5 42 p3.5 / t1 41 p0.4, ad4 pd2 p3.3 /exint1 pd1 pd0, ale pc7 pc6 pc5 usb- pc4 usb+ nc v cc gnd pc3 pc2 pc1 nc p4.7 / pwm4 p4.6 / pwm3 pc0 1 2 3 4 5 6 7 8 (1) 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pb0 p3.2 / exint0 pb1 p3.1 / txd pb2 p3.0 / rxd pb3 pb4 pb5 nc vref gnd reset pb6 pb7 rd, cntl1 p1.7 / adc3 psen, cntl2 wr, cntl0 p1.6 / adc2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pa7 pa6 p4.5 / pwm2 pa5 p4.4 / pwm1 pa4 p4.3 / pwm0 pa3 gnd p4.2 / dcc vsync p4.1 / ddc scl pa2 p4.0 / ddc sda pa1 pa0 ad0, p0.0 ad1, p0.1 ad2, p0.2 ad3, p0.3 p3.4 / t0 ai05791b
m psd323x 14/176 table 2. 80-pin package pin description port pin signal name pin no. in/out function basic alternate p0.0 ad0 36 i/o external bus multiplexed address/data bus a1/d1 p0.1 ad1 37 i/o multiplexed address/data bus a0/d0 p0.2 ad2 38 i/o multiplexed address/data bus a2/d2 p0.3 ad3 39 i/o multiplexed address/data bus a3/d3 p0.4 ad4 41 i/o multiplexed address/data bus a4/d4 p0.5 ad5 43 i/o multiplexed address/data bus a5/d5 p0.6 ad6 45 i/o multiplexed address/data bus a6/d6 p0.7 ad7 47 i/o multiplexed address/data bus a7/d7 p1.0 t2 52 i/o general i/o port pin timer 2 count input p1.1 t2ex 54 i/o general i/o port pin timer 2 trigger input p1.2 rxd2 56 i/o general i/o port pin 2nd uart receive p1.3 txd2 58 i/o general i/o port pin 2nd uart transmit p1.4 adc0 59 i/o general i/o port pin adc channel 0 input p1.5 adc1 60 i/o general i/o port pin adc channel 1 input p1.6 adc2 61 i/o general i/o port pin adc channel 2 input p1.7 adc3 64 i/o general i/o port pin adc channel 3 input p2.0 a8 51 i/o external bus, address a8 p2.1 a9 53 i/o external bus, address a9 p2.2 a10 55 i/o external bus, address a10 p2.3 a11 57 i/o external bus, address a11 p3.0 rxd1 75 i/o general i/o port pin uart receive p3.1 txd1 77 i/o general i/o port pin uart transmit p3.2 into 79 i/o general i/o port pin interrupt 0 input / timer0 gate control p3.3 int1 2 i/o general i/o port pin interrupt 1 input / timer1 gate control p3.4 t0 40 i/o general i/o port pin counter 0 input p3.5 t1 42 i/o general i/o port pin counter 1 input p3.6 sda1 44 i/o general i/o port pin i 2 c bus serial data i/o p3.7 scl1 46 i/o general i/o port pin i 2 c bus clock i/o p4.0 sda2 33 i/o general i/o port pin i 2 c serial data i/o for ddc interface p4.1 scl2 31 i/o general i/o port pin i 2 c clock i/o for ddc interface p4.2 vsync 30 i/o general i/o port pin vsync input for ddc interface
15/176 m psd323x p4.3 pwm0 27 i/o general i/o port pin 8-bit pulse width modulation output 0 p4.4 pwm1 25 i/o general i/o port pin 8-bit pulse width modulation output 1 p4.5 pwm2 23 i/o general i/o port pin 8-bit pulse width modulation output 2 p4.6 pwm3 19 i/o general i/o port pin 8-bit pulse width modulation output 3 p4.7 pwm4 18 i/o general i/o port pin programmable 8-bit pulse width modulation output 4 usb- 8 i/o usb pin pull-up resistor required (2k w for 3v devices, 7.5k w for 5v devices) for all devices, with or without usb function. usb+ 10 i/o usb pin avref 70 o reference voltage input for adc rd_ 65 o read signal, external bus wr_ 62 o write signal, external bus psen_ 63 o psen signal, external bus ale 4 o address latch signal, external bus reset_ 68 i active low reset input xtal1 48 i oscillator input pin for system clock xtal2 49 o oscillator output pin for system clock pa0 35 i/o general i/o port pin 1. pld macro-cell outputs 2. pld inputs 3. latched address out (a0-a7) 4. peripheral i/o mode pa1 34 i/o general i/o port pin pa2 32 i/o general i/o port pin pa3 28 i/o general i/o port pin pa4 26 i/o general i/o port pin pa5 24 i/o general i/o port pin pa6 22 i/o general i/o port pin pa7 21 i/o general i/o port pin port pin signal name pin no. in/out function basic alternate
m psd323x 16/176 52 pin package i/o port the 52-pin package members of the m psd323x devices have the same port pins as those of the 80-pin package except: n port 0 (p0.0-p0.7, external address/data bus ad0-ad7) n port 2 (p2.0-p2.3, external address bus a8- a11) n port a (pa0-pa7) n port d (pd2) n bus control signal (rd,wr,psen,ale) pin 5 requires a pull-up resistor (2k w for 3v de- vices, 7.5k w for 5v devices) for all devices, with or without usb function. pb0 80 i/o general i/o port pin 1. pld macro-cell outputs 2. pld inputs 3. latched address out (a0-a7) pb1 78 i/o general i/o port pin pb2 76 i/o general i/o port pin pb3 74 i/o general i/o port pin pb4 73 i/o general i/o port pin pb5 72 i/o general i/o port pin pb6 67 i/o general i/o port pin pb7 66 i/o general i/o port pin pc0 tms 20 i jtag pin 1. pld macro-cell outputs 2. pld inputs 3. sram stand by voltage input (v stby ) 4. sram battery-on indicator (pc4) 5. jtag pins are dedicated pins pc1 tck 16 i jtag pin pc2 v stby 15 i/o general i/o port pin pc3 tstat 14 i/o general i/o port pin pc4 terr 9 i/o general i/o port pin pc5 tdi 7 i jtag pin pc6 tdo 6 o jtag pin pc7 5 i/o general i/o port pin pd1 clkin 3 i/o general i/o port pin 1. pld i/o 2. clock input to pld and apd pd2 csi 1 i/o general i/o port pin 1. pld i/o 2. chip select to psd module vcc 12 vcc 50 gnd 13 gnd 29 gnd 69 nc 11 nc 17 nc 71 port pin signal name pin no. in/out function basic alternate
17/176 m psd323x architecture overview memory organization the m psd323x devices's standard 8032 core has separate 64kb address spaces for program memory and data memory. program memory is where the 8032 executes instructions from. data memory is used to hold data variables. flash memory can be mapped in either program or data space. the flash memory consists of two flash memory blocks: the main flash (1 or 2mbit) and the secondary flash (256kbit). except during flash memory programming or update, flash memory can only be read, not written to. a page register is used to access memory beyond the 64k bytes address space. refer to the psd mod- ule for details on mapping of the flash memory. the 8032 core has two types of data memory (in- ternal and external) that can be read and written. the internal sram consists of 256 bytes, and in- cludes the stack area. the sfr (special function registers) occupies the upper 128 bytes of the internal sram, the reg- isters can be accessed by direct addressing only. there are two separate blocks of external sram inside the m psd323x devices: one 256 bytes block is assigned for ddc data storage. another 8k bytes resides in the psd module that can be mapped to any address space defined by the user. figure 5. memory map and address space registers the 8032 has several registers; these are the pro- gram counter (pc), accumulator (a), b register (b), the stack pointer (sp), the program status word (psw), general purpose registers (r0 to r7), and dptr (data pointer register). figure 6. 8032 mcu registers ai06635 secondary flash flash main 32kb 128kb or 256kb ff 7f 0 ffff (ddc) 8kb 256b int. ram ext. ram ext. ram addressing indirect indirect direct or addressing addressing direct sfr internal ram space (256 bytes) ff00 external ram space (movx) flash memory space ai06636 accumulator b register stack pointer program counter program status word general purpose register (bank0-3) data pointer register pch dptr(dph) a b sp pcl psw r0-r7 dptr(dpl)
m psd323x 18/176 accumulator. the accumulator is the 8-bit gen- eral purpose register, used for data operation such as transfer, temporary saving, and conditional tests. the accumulator can be used as a 16-bit register with b register as shown below. figure 7. configuration of ba 16-bit registers b register. the b register is the 8-bit general purpose register, used for an arithmetic operation such as multiply, division with accumulator stack pointer. the stack pointer register is 8 bits wide. it is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the stack pointer is initialized to 07h after reset. this causes the stack to begin at location 08h. figure 8. stack pointer program counter. the program counter is a 16- bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pch:00h, pcl:00h). program status word. the program status word (psw) contains several bits that reflect the current state of the cpu and select internal ram (00h to 1fh: bank0 to bank3). the psw is de- scribed in figure 9, page 19. it contains the carry flag, the auxiliary carry flag, the half carry (for bcd operation), the general purpose flag, the register bank select flags, the overflow flag, and parity flag. [carry flag, cy]. this flag stores any carry or not borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruc- tion or rotate instruction. [auxiliary carry flag, ac]. after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. [register bank select flags, rs0, rs1]. this flags select one of four bank(00~07h:bank0, 08~0fh:bank1, 10~17h:bank2, 17~1fh:bank3) in internal ram. [overflow flag, ov]. this flag is set to '1' when an overflow occurs as the result of an arithmetic oper- ation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127 (7fh) or -128 (80h). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [parity flag, p]. this flag reflect on number of ac- cumulator's 1. if number of accumulator's 1 is odd, p=0. otherwise p=1. sum of adding accumulator's 1 to p is always even. r0~r7. general purpose 8-bit registers that are locked in the lower portion of internal data area. data pointer register. data pointer register is 16-bit wide which consists of two-8bit registers, dph and dpl. this register is used as a data pointer for the data transmission with external data memory in the psd module. ai06637 two 8-bit registers can be used as a obao 16-bit registers a b a b ai06638 sp (stack pointer) could be in 00h-ffh sp 00h stack area (30h-ffh) 00h-ffh hardware fixed bit 15 bit 0 bit 8 bit 7
19/176 m psd323x figure 9. psw (program status word) register program memory the program memory consists of two flash mem- ory: 128 kbyte (or 256 kbyte) main flash and 32 kbyte of secondary flash. the flash memory can be mapped to any address space as defined by the user in the psdsoft tool. it can also be mapped to data memory space during flash memory update or programming. after reset, the cpu begins execution from loca- tion 0000h. as shown in figure 10, each interrupt is assigned a fixed location in program memory. the interrupt causes the cpu to jump to that loca- tion, where it commences execution of the service routine. external interrupt 0, for example, is as- signed to location 0003h. if external interrupt 0 is going to be used, its service routine must begin at location 0003h. if the interrupt is not going to be used, its service location is available as general purpose pro-gram memory. the interrupt service locations are spaced at 8- byte intervals: 0003h for external interrupt 0, 000bh for timer 0, 0013h for external interrupt 1, 001bh for timer 1 and so forth. if an interrupt ser- vice routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. longer service routines can use a jump instruction to skip over subsequent in- terrupt locations, if other interrupts are in use. data memory the internal data memory is divided into four phys- ically separated blocks: 256 bytes of internal ram, 128 bytes of special function registers (sfrs) areas, 256 bytes of external ram (xram-ddc) and 8k bytes (xram-psd) in the psd module. ram four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, con- tain 128 directly addressable bit locations. the stack depth is only limited by the available internal ram space of 256 bytes. figure 10. interrupt location of program memory xram-ddc the 256 bytes of xram-ddc used to support ddc interface is also available for system usage by indirect addressing through the address pointer ddcadr and data i/o buffer rambuf. the ad- dress pointer (ddcadr) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to ddc interface part). however, it is also possible to address the ram through movx command as normally used in the internal ram extension of 80c51 deriva- tives. xram-ddc ff00 to ffff is directly ad- dressable as external data memory locations ff00 to ffff via movx-dptr instruction or via movx-ri instruction. when xram-ddc is dis- abled, the address space ff00 to ffff can be as- signed to other resources. xram-psd the 8k bytes of xram-psd resides in the psd module and can be mapped to any address space through the dpld (decoding pld) as defined by the user in psdsoft development tool. the xram- psd has a battery backup feature that allow the data to be retained in the event of a power lost. the battery is connected to the port c pc2 pin. this pin must be configured in psdsoft to be bat- tery back-up. ai06639 cy reset value 00h parity flag bit not assigned overflow flag register bank select flags (to select bank0-3) carry flag auxillary carry flag general purpose flag ac fo rs1 rs0 ov p msb lsb psw ai06640 0000h reset 8 bytes ? ? ? ? ? interrupt location 0003h 000bh 0013h 008bh ? ? ? ?
m psd323x 20/176 sfr the sfrs can only be addressed directly in the address range from 80h to ffh. table 15, page 32 gives an overview of the special function regis- ters. sixteen address in the sfrs space are both- byte and bit-addressable. the bit-addressable sfrs are those whose address ends in 0h and 8h. the bit addresses in this area are 80h to ffh. table 3. ram address addressing modes the addressing modes in m psd323x devices in- struction set are as follows n direct addressing n indirect addressing n register addressing n register-specific addressing n immediate constants addressing n indexed addressing (1) direct addressing. in a direct addressing the operand is specified by an 8-bit address field in the instruction. only internal data ram and sfrs (80~ffh ram) can be directly addressed. example: mov a, 3eh ; a <----- ram[3e] figure 11. direct addressing (2) indirect addressing. in indirect addressing the instruction specifies a register which contains the address of the operand. both internal and ex- ternal ram can be indirectly addressed. the ad- dress register for 8-bit addresses can be r0 or r1 of the selected register bank, or the stack pointer. the address register for 16-bit addresses can only be the 16-bit adata pointero register, dptr. example: mov @r1, #40 h ;[r1] <-----40h figure 12. indirect addressing byte address (in hexadecimal) byte address (in decimal) ffh 255 30h 48 msb bit address (hex) lsb 2fh 7f 7e 7d 7c 7b 7a 79 78 47 2eh 77 76 75 74 73 72 71 70 46 2dh 6f 6e 6d 6c 6b 6a 69 68 45 2ch 67 66 65 64 63 62 61 60 44 2bh 5f 5e 5d 5c 5b 5a 59 58 43 2ah 57 56 55 54 53 52 51 50 42 29h 4f 4e 4d 4c 4b 4a 49 48 41 28h 47 46 45 44 43 42 41 40 40 27h 3f 3e 3d 3c 3b 3a 39 38 39 26h 37 36 35 34 33 32 31 30 38 25h 2f 2e 2d 2c 2b 2a 29 28 37 24h 27 26 25 24 23 22 21 20 36 23h 1f 1e 1d 1c 1b 1a 19 18 35 22h 17 16 15 14 13 12 11 10 34 21h 0f 0e 0d 0c 0b 0a 09 08 33 20h 07 06 05 04 03 02 01 00 32 1fh register bank 3 31 18h 24 17h register bank 2 23 10h 16 0fh register bank 1 15 08h 8 07h register bank 0 7 00h 0 ai06641 3eh program memory 04 a ai06642 r1 55h program memory 55 40h
21/176 m psd323x (3) register addressing. the register banks, containing registers r0 through r7, can be ac- cessed by certain instructions which carry a 3-bit register specification within the opcode of the in- struction. instructions that access the registers this way are code efficient, since this mode elimi- nates an address byte. when the instruction is ex- ecuted, one of four banks is selected at execution time by the two bank select bits in the psw. example: mov psw, #0001000b ; select bank0 mov a, #30h mov r1, a (4) register-specific addressing. some in- structions are specific to a certain register. for ex- ample, some instructions always operate on the accumulator, or data pointer, etc., so no address byte is needed to point it. the opcode itself does that. (5) immediate constants addressing. the val- ue of a constant can follow the opcode in program memory. example: mov a, #10h. (6) indexed addressing. only program memory can be accessed with indexed addressing, and it can only be read. this addressing mode is intend- ed for reading look-up tables in program memory. a 16-bit base register (either dptr or pc) points to the base of the table, and the accumulator is set up with the table entry number. the address of the table entry in program memory is formed by add- ing the accumulator data to the base pointer. example: movc a, @a+dptr figure 13. indexed addressing arithmetic instructions the arithmetic instructions is listed in table 4, page 22. the table indicates the addressing modes that can be used with each instruction to access the operand. for example, the add a, instruction can be written as: add a, 7fh (direct addressing) add a, @r0 (indirect addressing) add a, r7 (register addressing) add a, #127 (immediate constant) note: any byte in the internal data memory space can be incremented without going through the ac- cumulator. one of the inc instructions operates on the 16-bit data pointer. the data pointer is used to generate 16-bit addresses for external memory, so being able to increment it in one 16-bit operations is a useful feature. the mul ab instruction multiplies the accumula- tor by the data in the b register and puts the 16-bit product into the concatenated b and accumulator registers. the div ab instruction divides the accumulator by the data in the b register and leaves the 8-bit quo- tient in the accumulator, and the 8-bit remainder in the b register. in shift operations, dividing a number by 2n shifts its ano bits to the right. using div ab to perform the division completes the shift in 4?s and leaves the b register holding the bits that were shifted out. the daa instruction is for bcd arithmetic opera- tions. in bcd arithmetic, add and addc instruc- tions should always be followed by a daa operation, to ensure that the result is also in bcd. note: daa will not convert a binary number to bcd. the daa operation produces a meaningful result only as the second step in the addition of two bcd bytes. ai06643 3eh program memory acc dptr 3ah 1e73h
m psd323x 22/176 table 4. arithmetic instructions logical instructions table 5, page 23 shows list of m psd323x devices logical instructions. the instructions that perform boolean operations (and, or, exclusive or, not) on bytes perform the operation on a bit-by- bit basis. that is, if the accumulator contains 00110101b and byte contains 01010011b, then: anl a, will leave the accumulator holding 00010001b. the addressing modes that can be used to access the operand are listed in table 5. the anl a, instruction may take any of the forms: anl a,7fh(direct addressing) anl a, @r1 (indirect addressing) anl a,r6 (register addressing) anl a,#53h (immediate constant) note: boolean operations can be performed on any byte in the internal data memory space with- out going through the accumulator. the xrl , #data instruction, for example, offers a quick and easy way to invert port bits, as in xrl p1, #0ffh. if the operation is in response to an interrupt, not using the accumulator saves the time and effort to push it onto the stack in the service routine. the rotate instructions (rl a, rlc a, etc.) shift the accumulator 1 bit to the left or right. for a left rotation, the msb rolls into the lsb position. for a right rotation, the lsb rolls into the msb position. the swap a instruction interchanges the high and low nibbles within the accumulator. this is a useful operation in bcd manipulations. for exam- ple, if the accumulator contains a binary number which is known to be less than 100, it can be quick- ly converted to bcd by the following code: move b,#10 div ab swap a add a,b dividing the number by 10 leaves the tens digit in the low nibble of the accumulator, and the ones digit in the b register. the swap and add instruc- tions move the tens digit to the high nibble of the accumulator, and the ones digit to the low nibble. mnemonic operation addressing modes dir. ind. reg. imm add a, a = a + x x x x addc a, a = a + + c x x x x subb a, a = a c x x x x inc a = a + 1 accumulator only inc = + 1 x x x inc dptr dptr = dptr + 1 data pointer only dec a = a 1 accumulator only dec = 1 x x x mul ab b:a = b x a accumulator and b only div ab a=int[a/b] b = mod[ a / b ] accumulator and b only da a decimal adjust accumulator only
23/176 m psd323x table 5. logical instructions mnemonic operation addressing modes dir. ind. reg. imm anl a, a = a .and. x x x x anl ,a a = .and. a x anl ,#data a = .and. #data x orl a, a = a .or. x x x x orl ,a a = .or. a x orl ,#data a = .or. #data x xrl a, a = a .xor. x x x x xrl ,a a = .xor. a x xrl ,#data a = .xor. #data x crl a a = 00h accumulator only cpl a a = .not. a accumulator only rl a rotate a left 1 bit accumulator only rlc a rotate a left through carry accumulator only rr a rotate a right 1 bit accumulator only rrc a rotate a right through carry accumulator only swap a swap nibbles in a accumulator only
m psd323x 24/176 data transfers internal ram. table 6 shows the menu of in- structions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. the mov , instruction allows data to be transferred between any two internal ram or sfr locations without going through the accumulator. remember, the upper 128 bytes of data ram can be accessed only by indirect ad- dressing, and sfr space only by direct address- ing. note: in m psd323x devices, the stack resides in on-chip ram, and grows upwards. the push in- struction first increments the stack pointer (sp), then copies the byte into the stack. push and pop use only direct addressing to identify the byte being saved or restored, but the stack itself is ac- cessed by indirect addressing using the sp regis- ter. this means the stack can go into the upper 128 bytes of ram, if they are implemented, but not into sfr space. the data transfer instructions include a 16-bit mov that can be used to initialize the data pointer (dptr) for look-up tables in program memory. the xch a, instruction causes the accu- mulator and ad-dressed byte to exchange data. the xchd a, @ri instruction is similar, but only the low nibbles are involved in the exchange. to see how xch and xchd can be used to facilitate data manipulations, consider first the problem of shifting and 8-digit bcd number two digits to the right. table 8 shows how this can be done using xch instructions. to aid in understanding how the code works, the contents of the registers that are holding the bcd number and the content of the accumulator are shown alongside each instruction to indicate their status after the instruction has been executed. after the routine has been executed, the accumu- lator contains the two digits that were shifted out on the right. doing the routine with direct movs uses 14 code bytes. the same operation with xchs uses only 9 bytes and executes almost twice as fast. to right-shift by an odd number of digits, a one-digit must be executed. table 9 shows a sample of code that will right-shift a bcd number one digit, using the xchd instruction. again, the contents of the registers holding the number and of the accumulator are shown along- side each instruction. table 6. data transfer instructions that access internal data memory space mnemonic operation addressing modes dir. ind. reg. imm mov a, a = x x x x mov ,a = a x x x mov , = x x x x mov dptr,#data16 dptr = 16-bit immediate constant x push inc sp; mov a@spo, x pop mov ,o@spo; dec sp x xch a, exchange contents of a and x x x xchd a,@ri exchange low nibbles of a and @ri x
25/176 m psd323x first, pointers r1 and r0 are set up to point to the two bytes containing the last four bcd digits. then a loop is executed which leaves the last byte, loca- tion 2eh, holding the last two digits of the shifted number. the pointers are decremented, and the loop is repeated for location 2dh. the cjne in- struction (compare and jump if not equal) is a loop control that will be described later. the loop executed from loop to cjne for r1 = 2eh, 2dh, 2ch, and 2bh. at that point the digit that was orig- inally shifted out on the right has propagated to lo- cation 2ah. since that location should be left with 0s, the lost digit is moved to the accumulator. table 7. shifting a bcd number two digits to the right (using direct movs: 14 bytes) table 8. shifting a bcd number two digits to the right (using direct xchs: 9 bytes) table 9. shifting a bcd number one digit to the right 2a 2b 2c 2d 2e acc mov a,2eh 00 12 34 56 78 78 mov 2eh,2dh 00 12 34 56 56 78 mov 2dh,2ch 00 12 34 34 56 78 mov 2ch,2bh 00 12 12 34 56 78 mov 2bh,#0 00 00 12 34 56 78 2a 2b 2c 2d 2e acc clr a 00 12 34 56 78 00 xch a,2bh 00 00 34 56 78 12 xch a,2ch 00 00 12 56 78 34 xch a,2dh 00 00 12 34 78 56 xch a,2eh 00 00 12 34 56 78 2a 2b 2c 2d 2e acc mov r1,#2eh 00 12 34 56 78 xx mov r0,#2dh 00 12 34 56 78 xx ; loop for r1 = 2eh loop: mov a,@r1 00 12 34 56 78 78 xchd a,@r0 00 12 34 58 78 76 swap a 00 12 34 58 78 67 mov @r1,a 00 12 34 58 67 67 dec r1 00 12 34 58 67 67 dec r0 00 12 34 58 67 67 cnje r1,#2ah,loop 00 12 34 58 67 67 ; loop for r1 = 2dh 00 12 38 45 67 45 ; loop for r1 = 2ch 00 18 23 45 67 23 ; loop for r1 = 2bh 08 01 23 45 67 01 clr a 0801234567 00 xch a,2ah 00 01 23 45 67 08
m psd323x 26/176 external ram. table 10 shows a list of the data transfer instructions that access external data memory. only indirect addressing can be used. the choice is whether to use a one-byte address, @ri, where ri can be either r0 or r1 of the se- lected register bank, or a two-byte address, @dtpr. note: in all external data ram accesses, the ac- cumulator is always either the destination or source of the data. lookup tables. table 11 shows the two instruc- tions that are available for reading lookup tables in program memory. since these instructions access only program memory, the lookup tables can only be read, not updated. the mnemonic is movc for amove constant.o the first movc instruction in table 11 can accommo- date a table of up to 256 entries numbered 0 through 255. the number of the desired entry is loaded into the accumulator, and the data pointer is set up to point to the beginning of the table. then: movc a, @a+dptr copies the desired table entry into the accumula- tor. the other movc instruction works the same way, except the program counter (pc) is used as the table base, and the table is accessed through a subroutine. first the number of the desired en-try is loaded into the accumulator, and the subroutine is called: mov a , entry number call table the subroutine atableo would look like this: table: movc a , @a+pc ret the table itself immediately follows the ret (re- turn) instruction is program memory. this type of table can have up to 255 entries, numbered 1 through 255. number 0 cannot be used, because at the time the movc instruction is executed, the pc contains the address of the ret instruction. an entry numbered 0 would be the ret opcode it- self. table 10. data transfer instruction that access external data memory space table 11. lookup table read instruction address width mnemonic operation 8 bits movx a,@ri read external ram @ri 8 bits movx @ri,a write external ram @ri 16 bits movx a,@dptr read external ram @dptr 16 bits movx @dptr,a write external ram @dptr mnemonic operation movc a,@a+dptr read program memory at (a+dptr) movc a,@a+pc read program memory at (a+pc)
27/176 m psd323x boolean instructions the m psd323x devices contain a complete bool- ean (single-bit) processor. one page of the inter- nal ram contains 128 address-able bits, and the sfr space can support up to 128 addressable bits as well. all of the port lines are bit-addressable, and each one can be treated as a separate single- bit port. the instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, or and and instructions. these kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software. the instruction set for the boolean processor is shown in table 12. all bits accesses are by direct addressing. bit addresses 00h through 7fh are in the lower 128, and bit ad-dresses 80h through ffh are in sfr space. note how easily an internal flag can be moved to a port pin: mov c,flag mov p1.0,c in this example, flag is the name of any addres- sable bit in the lower 128 or sfr space. an i/o line (the lsb of port 1, in this case) is set or cleared depending on whether the flag bit is '1' or '0.' the carry bit in the psw is used as the single-bit accumulator of the boolean processor. bit instruc- tions that refer to the carry bit as c assemble as carry-specific instructions (clr c, etc.). the car- ry bit also has a direct address, since it resides in the psw register, which is bit-addressable. note: the boolean instruction set includes anl and orl operations, but not the xrl (exclusive or) operation. an xrl operation is simple to im- plement in software. suppose, for example, it is re- quired to form the exclusive or of two bits: c = bit 1 .xrl. bit2 the software to do that could be as follows: mov c , bit1 jnb bit2, over cpl c over: (continue) first, bit 1 is moved to the carry. if bit2 = 0, then c now contains the correct result. that is, bit 1 .xrl. bit2 = bit1 if bit2 = 0. on the other hand, if bit2 = 1, c now contains the complement of the correct result. it need only be inverted (cpl c) to complete the operation. this code uses the jnb instruction, one of a series of bit-test instructions which execute a jump if the addressed bit is set (jc, jb, jbc) or if the ad- dressed bit is not set (jnc, jnb). in the above case, bit 2 is being tested, and if bit2 = 0, the cpl c instruction is jumped over. jbc executes the jump if the addressed bit is set, and also clears the bit. thus a flag can be tested and cleared in one operation. all the psw bits are directly addressable, so the parity bit, or the gen- eral-purpose flags, for example, are also available to the bit-test instructions. table 12. boolean instructions relative offset the destination address for these jumps is speci- fied to the assembler by a label or by an actual ad- dress in program memory. how-ever, the destination address assembles to a relative offset byte. this is a signed (two's complement) offset byte which is added to the pc in two's complement arithmetic if the jump is executed. the range of the jump is therefore -128 to +127 program memory bytes relative to the first byte fol- lowing the instruction. mnemonic operation anl c,bit c = a .and. bit anl c,/bit c = c .and. .not. bit orl c,bit c = a .or. bit orl c,/bit c = c .or. .not.bit mov c,bit c = bit mov bit,c bit = c clr c c = 0 clr bit bit = 0 setb c c = 1 setb bit bit = 1 cpl c c = .not. c cpl bit bit = .not. bit jc rel jump if c =1 jnc rel jump if c = 0 jb bit,rel jump if bit =1 jnb bit,rel jump if bit = 0 jbc bit,rel jump if bit = 1; clr bit
m psd323x 28/176 jump instructions table 13 shows the list of unconditional jump in- structions. the table lists a single ajmp addo in- struction, but in fact there are three sjmp, ljmp, and ajmp, which differ in the format of the desti- nation address. jmp is a generic mnemonic which can be used if the programmer does not care which way the jump is en-coded. the sjmp instruction encodes the destination ad- dress as a relative offset, as described above. the instruction is 2 bytes long, consisting of the op- code and the relative offset byte. the jump dis- tance is limited to a range of -128 to +127 bytes relative to the instruction following the sjmp. the ljmp instruction encodes the destination ad- dress as a 16-bit constant. the instruction is 3 bytes long, consisting of the opcode and two ad- dress bytes. the destination address can be any- where in the 64k program memory space. the ajmp instruction encodes the destination ad- dress as an 11-bit constant. the instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by an- other byte containing the low 8 bits of the destina- tion address. when the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the pc. the high 5 bits stay the same. hence the destination has to be within the same 2k block as the instruction following the ajmp. in all cases the programmer specifies the destina- tion address to the assembler in the same way: as a label or as a 16-bit constant. the assembler will put the destination address into the correct format for the given instruction. if the format required by the instruction will not support the distance to the specified destination address, a adestination out of rangeo message is written into the list file. the jmp @a+dptr instruction supports case jumps. the destination address is computed at ex- ecution time as the sum of the 16-bit dptr regis- ter and the accumulator. typically. dptr is set up with the address of a jump table. in a 5-way branch, for ex-ample, an integer 0 through 4 is loaded into the accumulator. the code to be exe- cuted might be as follows: mov dptr,#jump table mov a,index_number rl a jmp @a+dptr the rl a instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because each entry in the jump table is 2 bytes long: jump table: ajmp case 0 ajmp case 1 ajmp case 2 ajmp case 3 ajmp case 4 table 13 shows a single acall addro instruction, but there are two of them, lcall and acall, which differ in the format in which the subroutine address is given to the cpu. call is a generic mnemonic which can be used if the programmer does not care which way the address is encoded. the lcall instruction uses the 16-bit address for- mat, and the subroutine can be anywhere in the 64k program memory space. the acall instruc- tion uses the 11-bit format, and the subroutine must be in the same 2k block as the instruction fol- lowing the acall. in any case, the programmer specifies the subrou- tine address to the assembler in the same way: as a label or as a 16-bit constant. the assembler will put the address into the correct format for the giv- en instructions. subroutines should end with a ret instruction, which returns execution to the instruction following the call. reti is used to return from an interrupt service routine. the only difference between ret and reti is that reti tells the interrupt control system that the interrupt in progress is done. if there is no interrupt in progress at the time reti is executed, then the reti is functionally identical to ret. table 13. unconditional jump instructions mnemonic operation jmp addr jump to addr jmp @a+dptr jump to a+dptr call addr call subroutine at addr ret return from subroutine reti return from interrupt nop no operation
29/176 m psd323x table 14 shows the list of conditional jumps avail- able to the m psd323x devices user. all of these jumps specify the destination address by the rela- tive offset method, and so are limited to a jump dis- tance of -128 to +127 bytes from the instruction following the conditional jump instruction. impor- tant to note, however, the user specifies to the as- sembler the actual destination address the same way as the other jumps: as a label or a 16-bit con- stant. there is no zero bit in the psw. the jz and jnz instructions test the accumulator data for that con- dition. the djnz instruction (decrement and jump if not zero) is for loop control. to execute a loop n times, load a counter byte with n and terminate the loop with a djnz to the beginning of the loop, as shown below for n = 10: mov counter,#10 loop: (begin loop) ? ? ? (end loop) djnz counter, loop (continue) the cjne instruction (compare and jump if not equal) can also be used for loop control as in ta- ble 9. two bytes are specified in the operand field of the instruction. the jump is executed only if the two bytes are not equal. in the example of table 9 shifting a bcd number one digits to the right, the two bytes were data in r1 and the constant 2ah. the initial data in r1 was 2eh. every time the loop was executed, r1 was decre- mented, and the looping was to continue until the r1 data reached 2ah. another application of this instruction is in agreater than, less thano comparisons. the two bytes in the operand field are taken as unsigned integers. if the first is less than the second, then the carry bit is set (1). if the first is greater than or equal to the second, then the carry bit is cleared machine cycles a machine cycle consists of a sequence of six states, numbered s1 through s6. each state time lasts for two oscillator periods. thus, a machine cycle takes 12 oscillator periods or 1 m s if the oscil- lator frequency is 12mhz. refer to figure 14, page 30. each state is divided into a phase 1 half and a phase 2 half. state sequence in m psd323x de- vices shows that retrieve/execute sequences in states and phases for various kinds of instructions. normally two program retrievals are generated during each machine cycle, even if the instruction being executed does not require it. if the instruc- tion being executed does not need more code bytes, the cpu simply ignores the extra retrieval, and the program counter is not incremented. execution of a one-cycle instruction (figure 14, page 30) begins during state 1 of the machine cy- cle, when the opcode is latched into the instruction register. a second retrieve occurs during s4 of the same machine cycle. execution is complete at the end of state 6 of this machine cycle. the movx instructions take two machine cycles to execute. no program retrieval is generated dur- ing the second cycle of a movx instruction. this is the only time program retrievals are skipped. the retrieve/execute sequence for movx instruc- tion is shown in figure 14, page 30 (d). table 14. conditional jump instructions mnemonic operation addressing modes dir. ind. reg. imm jz rel jump if a = 0 accumulator only jnz rel jump if a 0 accumulator only djnz ,rel decrement and jump if not zero x x cjne a,,rel jump if a x x cjne ,#data,rel jump if #data x x
m psd323x 30/176 figure 14. state sequence in m psd323x devices osc. (xtal2) read opcode read next opcode read next opcode and discard read next opcode and discard read 2nd byte no fetch no fetch no ale s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 read opcode read next opcode s1 s2 s3 s4 s5 s6 read opcode read next opcode s1 s2 s3 s4 s5 s6 read next opcode and discard s1 s2 s3 s4 s5 s6 read next opcode and discard read next opcode and discard read opcode (movx) read next opcode s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 addr data access external memory ai06822 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 a. 1-byte, 1-cycle instruction, e.g. inc a b. 2-byte, 1-cycle instruction, e.g. add a, adrs c. 1-byte, 2-cycle instruction, e.g. inc dptr d. 1-byte, 2-cycle movx instruction
31/176 m psd323x m psd3200 hardware description the m psd323x devices has a modular architec- ture with two main functional modules: the mcu module and the psd module. the mcu module consists of a standard 8032 core, peripherals and other system supporting functions. the psd mod- ule provides configurable program and data mem- ories to the 8032 cpu core. in addition, it has its own set of i/o ports and a pld with 16 macrocells for general logic implementation. ports a,b,c, and d are general purpose programmable i/o ports that have a port architecture which is different from ports 0-4 in the mcu module. the psd module communicates with the cpu core through the internal address, data bus (a0- a15, d0-d7) and control signals (rd_, wr_, psen_ , ale, reset_). the user defines the de- coding pld in the psdsoft development tool and can map the resources in the psd module to any program or data address space. figure 15. m psd323x devices functional modules ai06619c 4 channel adc 1mb or 2mb main flash decode pld 64kb sram cpld - 16 macrocells jtag isp port 1 port 3 2 uarts interrupt 3 timer / counters 256 byte sram 8032 core port 3, uart, intr, timers,i 2 c psd internal bus 8032 internal bus usb & transceiver port 1, timers and 2nd uart and adc ddc w/ 256 byte sram pwm 5 channels port 4 pwm and ddc dedicated usb pins port a & b, pld i/o and gpio port d gpio port c, jtag, pld i/o and gpio vcc, gnd, xtal 256kb secondary flash dedicated pins i2c port 0, 2 ext. bus reset logic lvd & wdt bus interface reset d0-d7 a0-a15 rd,psen wr,ale page register psd module mcu module
m psd323x 32/176 mcu module discription this section provides a detail description of the mcu module system functions and peripherals, including: special function registers timers/counter interrupts pwm supervisory function (lvd and watchdog) usart power saving modes i 2 c bus on-chip oscillator adc i/o ports usb special function registers a map of the on-chip memory area called the spe- cial function register (sfr) space is shown in ta- ble 15. note: in the sfrs not all of the addresses are oc- cupied. unoccupied addresses are not implement- ed on the chip. read accesses to these addresses will in general return random data, and write accesses will have no effect. user soft- ware should write '0s' to these unimplemented lo- cations. table 15. sfr memory map note: 1. register can be bit addressing f8 ff f0 b 1 f7 e8 uista 1 uien ucon0 ucon1 ucon2 usta uadr udr0 ef e0 acc 1 uscl udt1 udt0 e7 d8 s1con 1 s1sta s1dat s1adr s2con s2sta s2dat s2adr df d0 psw 1 s1setup s2setup rambuf ddcdat ddcadr ddccon d7 c8 t2con 1 t2mod rcap2l rcap2h tl2 th2 cf c0 p4 1 c7 b8 ip 1 bf b0 p3 1 pscl0l pscl0h pscl1l pscl1h ipa b7 a8 ie 1 pwm4p pwm4w wdkey af a0 p2 1 pwmcon pwm0 pwm1 pwm2 pwm3 wdrst iea a7 98 scon sbuf scon2 sbuf2 9f 90 p1 1 p1sfs p3sfs p4sfs ascl adat acon 97 88 tcon 1 tmod tl0 tl1 th0 th1 8f 80 p0 1 sp dpl dph pcon 87
33/176 m psd323x table 16. list of all sfr sfr addr reg name bit register name reset value comments 7 654 3210 80 p0 ff port 0 81 sp 07 stack ptr 82 dpl 00 data ptr low 83 dph 00 data ptr high 87 pcon smod smod1 lvren adsfint rclk1 tclk1 pd idle 00 power ctrl 88 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 timer / cntr control 89 tmod gate c/t m1 m0 gate c/t m1 m0 00 timer / cntr mode control 8a tl0 00 timer 0 low 8b tl1 00 timer 1 low 8c th0 00 timer 0 high 8d th1 00 timer 1 high 90 p1 ff port 1 91 p1sfs p1s7 p1s6 p1s5 p1s4 00 port 1 select register 93 p3sfs p3s7 p3s6 00 port 3 select register 94 p4sfs p4s7 p4s6 p4s5 p4s4 p4s3 p4s2 p4s1 p4s0 00 port 4 select register 95 ascl 00 8-bit prescaler for adc clock 96 adat adat7 adat6 adat5 adat4 adat3 adat2 adat1 adat0 00 adc data register 97 acon aden ads1 ads0 adst adsf 00 adc control register 98 scon sm0 sm1 sm2 ren tb8 rb8 ti ri 00 serial control register 99 sbuf 00 serial buffer 9a scon2 sm0 sm1 sm2 ren tb8 rb8 ti ri 00 2nd uart ctrl register 9b sbuf2 00 2nd uart serial buffer a0 p2 ff port 2 a1 pwmcon pwml pwmp pwme cfg4 cfg3 cfg2 cfg1 cfg0 00 pwm control polarity
m psd323x 34/176 a2 pwm0 00 pwm0 output duty cycle a3 pwm1 00 pwm1 output duty cycle a4 pwm2 00 pwm2 output duty cycle a5 pwm3 00 pwm3 output duty cycle a6 wdrst 00 watch dog reset a7 iea eddc es2 ei 2 c eusb 00 interrupt enable (2nd) a8 ie ea - et2 es et1 ex1 et0 ex0 00 interrupt enable a9 aa pwm4p 00 pwm 4 period ab pwm4w 00 pwm 4 pulse width ae wdkey 00 watch dog key register b0 p3 ff port 3 b1 pscl0l 00 prescaler 0 low (8-bit) b2 pscl0h 00 prescaler 0 high (8-bit) b3 pscl1l 00 prescaler 1 low (8-bit) b4 pscl1h 00 prescaler 1 high (8-bit) b7 ipa pddc ps2 pi2c pusb 00 interrupt priority (2nd) b8 ip pt2 ps pt1 px1 pt0 px0 00 interrupt priority c0 p4 ff new port 4 c8 t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00 timer 2 control c9 t2mod dcen 00 timer 2 mode sfr addr reg name bit register name reset value comments 7 654 3210
35/176 m psd323x ca rcap2l 00 timer 2 reload low cb rcap2h 00 timer 2 reload high cc tl2 00 timer 2 low byte cd th2 00 timer 2 high byte d0 psw cy ac fo rs1 rs0 ov p 00 program status word d1 s1setup 00 ddc i 2 c (s1) setup d2 s2setup 00 i 2 c (s2) setup d4 rambuf xx ddc ram buffer d5 ddcdat 00 ddc data xmit register d6 ddcadr 00 addr pointer register d7 ddccon e ex_dat swenb ddc_ax ddcint ddc1en swhint m0 00 ddc control register d8 s1con cr2 eni1 sta sto addr aa cr1 cr0 00 ddc i 2 c control reg d9 s1sta gc stop intr tx-md bbusy blost ack_r slv 00 ddc i 2 c status da s1dat 00 data hold register db s1adr 00 ddc i 2 c address dc s2con cr2 en1 sta sto addr aa cr1 cr0 00 i 2 c bus control reg dd s2sta gc stop intr tx-md bbusy blost ack_r slv 00 i 2 c bus status de s2dat 00 data hold register df s2adr 00 i 2 c address e0 acc 00 accumulator e1 uscl 00 8-bit prescaler for usb logic e6 udt1 udt1.7 udt1.6 udt1.5 udt1.4 udt1.3 udt1.2 udt1.1 udt1.0 00 usb endpt1 data xmit sfr addr reg name bit register name reset value comments 7 654 3210
m psd323x 36/176 e7 udt0 udt0.7 udt0.6 udt0.5 udt0.4 udt0.3 udt0.2 udt0.1 udt0.0 00 usb endpt0 data xmit e8 uista suspnd e rstf txd0f rxd0f rxd1f eopf resumf 00 usb interrupt status e9 uien suspndi e rste rstfie txd0ie rxd0ie txd1ie eopie resumi e 00 usb interrupt enable ea ucon0 tseq0 stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 00 usb endpt0 xmit control eb ucon1 tseq1 ep12sel e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 00 usb endpt1 xmit control ec ucon2 e e e sout ep2e ep1e stall2 stall1 00 usb control register ed usta rseq setup in out rp0siz3 rp0siz2 rp0siz1 rp0siz0 00 usb endpt0 status ee uadr usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 00 usb address register ef udr0 udr0.7 udr0.6 udr0.5 udr0.4 udr0.3 udr0.2 udr0.1 udr0.0 00 usb endpt0 data recv f0 b 00 b register sfr addr reg name bit register name reset value comments 7 654 3210
37/176 m psd323x table 17. psd module register address offset csiop addr offset register name bit register name reset value comments 7 6 5 432 1 0 00 data in (port a) reads port pins as input 02 control (port a) configure pin between i/o or address out mode. bit = 0 selects i/ o 00 04 data out (port a) latched data for output to port pins, i/o output mode 00 06 direction (port a) configures port pin as input or output. bit = 0 selects input 00 08 drive (port a) configures port pin between cmos, open drain or slew rate. bit = 0 selects cmos 00 0a input macrocell (port a) reads latched value on input macrocells 0c enable out (port a) reads the status of the output enable control to the port pin driver. bit = 0 indicates pin is in input mode. 01 data in (port b) 03 control (port b) 00 05 data out (port b) 00 07 direction (port b) 00 09 drive (port b) 00 0b input macrocell (port b) 0d enable out (port b) 10 data in (port c) 12 data out (port c) 00 14 direction (port c) 00 16 drive (port c) 00 18 input macrocell (port c) 1a enable out (port c) 11 data in (port d) * * * * * * only bit 1 and 2 are used 13 data out (port d) * * * * * * 00 only bit 1 and 2 are used 15 direction (port d) * * * * * * 00 only bit 1 and 2 are used 17 drive (port d) * * * * * * 00 only bit 1 and 2 are used 1b enable out (port d) ***** * only bit 1 and 2 are used 20 output macrocells ab
m psd323x 38/176 note: (register address = csiop address + address offset; where csiop address is defined by user in psdsoft) * indicates bit is not used and need to set to '0.' 21 output macrocells bc 22 mask macrocells ab 23 mask macrocells bc c0 primary flash protection sec7_ prot sec6_ prot sec5_ prot sec4_ prot sec3_ prot sec2_ prot sec1_ prot sec0_ prot bit = 1 sector is protected c2 secondary flash protection security _bit *** sec3_ prot sec2_ prot sec1_ prot sec0_ prot security bit = 1 device is secured b0 pmmr0 * * pld mcells clk pld array- clk pld turbo * apd enable *00 control pld power consumption b4 pmmr2 * pld array wrh pld arrayal e pld array cntl2 pld array cntl1 pld array cntl0 **00 blocking inputs to pld array e0 page 00 page register e2 vm periph- mode ** fl_da ta boot_ data fl_co de boot_c ode sr_co de configure 8032 program and data space csiop addr offset register name bit register name reset value comments 7 6 5 432 1 0
39/176 m psd323x interrupt system there are interrupt requests from 10 sources as follows. n int0 external interrupt n 2nd usart interrupt n timer0 interrupt n i 2 c interrupt n int1 external interrupt (or adc interrupt) n ddc interrupt n timer1 interrupt n usb interrupt n usart interrupt n timer2 interrupt external int0 n the int0 can be either level-active or transition- active depending on bit it0 in register tcon. the flag that actually generates this interrupt is bit ie0 in tcon. n when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. n if the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. timer 0 and 1 interrupts n timer0 and timer1 interrupts are generated by tf0 and tf1 which are set by an overflow of their respective timer/counter registers (except for timer0 in mode 3). n these flags are cleared by the internal hardware when the interrupt is serviced. timer 2 interrupt n timer2 interrupt is generated by tf2 which is set by an overflow of timer2. this flag has to be cleared by the software - not by hardware. n it is also generated by the t2ex signal (timer 2 external interrupt p1.1) which is controlled by exen2 and exf2 bits in the t2con register. this is the definition of timer 2 as per 90c320 definition. i 2 c interrupt n the interrupt of the i 2 c is generated by bit intr in the register s2sta. n this flag is cleared by hardware. external int1 n the int1 can be either level active or transition active depending on bit it1 in register tcon. the flag that actually generates this interrupt is bit ie1 in tcon. n when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. n if the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. n the adc can take over the external int1 to generate an interrupt on conversion being completed ddc interrupt n the ddc interrupt is generated either by bit intr in the s1sta register for dc2b protocol or by bit ddc interrupt in the ddccon register for ddc1 protocol or by bit swhint bit in the ddccon register when ddc protocol is changed from ddc1 to ddc2. n flags except the intr have to be cleared by the software. intr flag is cleared by hardware. usb interrupt n the usb interrupt is generated when endpoint0 has transmitted a packet or received a packet, when endpoint1 or endpoint2 has transmitted a packet, when the suspend or resume state is detected and every eop received. n when the usb interrupt is generated, the corresponding request flag must be cleared by software. the interrupt service routine will have to check the various usb registers to determine the source and clear the corresponding flag. n please see the dedicated interrupt control registers for the usb peripheral for more information.
m psd323x 40/176 usart interrupt n the usart interrupt is generated by ri (receive interrupt) or ti (transmit interrupt). n when the usart interrupt is generated, the corresponding request flag must be cleared by software. the interrupt service routine will have to check the various usart registers to determine the source and clear the corresponding flag. n both usart's are identical, except for the additional interrupt controls in the bit 4 of the additional interrupt control registers (a7h, b7h) figure 16. interrupt system ai06646 int0 usart timer 0 i2c int1 ddc timer 1 usb 2nd usart timer 2 high low interrupt polling interrupt sources ie / ip / ipa priority global enable
41/176 m psd323x table 18. sfr register interrupt priority structure each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority special function register ip and ipa. 0 = low priority 1 = high priority a low priority interrupt may be interrupted by a high priority interrupt level interrupt. a high priority interrupt routine cannot be interrupted by any oth- er interrupt source. if two interrupts of different pri- ority occur simultaneously, the high priority level request is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling se- quence. interrupts enable structure each interrupt source can be individually enabled or disabled by setting or clearing a bit in the inter- rupt enable special function register ie and iea. all interrupt source can also be globally disabled by clearing bit ea in ie. table 19. priority levels table 20. description of the ie bits sfr addr reg name bit register name reset value comments 76543210 a7 iea eddc e e es2 e e ei 2 c eusb 00 interrupt enable (2nd) a8 ie ea e et2 es et1 ex1 et0 ex0 00 interrupt enable b7 ipa pddc e e ps2 e e pi 2 c pusb 00 interrupt priority (2nd) b8 ip e e pt2 ps pt1 px1 pt0 px0 00 interrupt priority source priority with level int0 0 (highest) 2nd usart 1 timer0 2 i c 3 int1 4 ddc 5 timer1 6 usb 7 1st usart 8 timer2+exf2 9 (lowest) bit symbol function 7ea disable all interrupts: 0: no interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit 6 e reserved 5 et2 enable timer2 interrupt 4 es enable usart interrupt 3 et1 enable timer1 interrupt 2 ex1 enable external interrupt (int1) 1 et0 enable timer0 interrupt 0 ex0 enable external interrupt (int0)
m psd323x 42/176 table 21. description of the iea bits table 22. description of the ip bits table 23. description of the ipa bits bit symbol function 7 eddc enable ddc interrupt 6 e not used 5 e not used 4 es2 enable 2nd usart interrupt 3 e not used 2 e not used 1 ei2c enable i c interrupt 0 eusb enable usb interrupt bit symbol function 7 e reserved 6 e reserved 5 pt2 timer2 interrupt priority level 4 ps usart interrupt priority level 3 pt1 timer1 interrupt priority level 2 px1 external interrupt (int1) priority level 1 pt0 timer0 interrupt priority level 0 px0 external interrupt (int0) priority level bit symbol function 7 pddc ddc interrupt priority level 6 e not used 5 e not used 4 ps2 2nd usart interrupt priority level 3 e not used 2 e not used 1 pi2c i c interrupt priority level 0 pusb usb interrupt priority level
43/176 m psd323x how interrupts are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during fol- lowing machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service rou- tine, provided this h/w generated lcall is not blocked by any of the following conditions: n an interrupt of equal priority or higher priority level is already in progress. n the current machine cycle is not the final cycle in the execution of the instruction in progress. n the instruction in progress is reti or any access to the interrupt priority or interrupt enable registers. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cy- cle. note: if an interrupt flag is active but being re- sponded to for one of the above mentioned condi- tions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the inter- rupt flag was once active but not serviced is not re- membered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate service routine. the hardware gener- ated lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that de- pends on the source of the interrupt being vec- tored to as shown in table 24. execution proceeds from that location until the reti instruction is encountered. the reti instruc- tion informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note: a simple ret instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future inter- rupts impossible. table 24. vector addresses source vector address int0 0003h 2nd usart 004bh timer0 000bh i c 0043h int1 0013h ddc 003bh timer1 001bh usb 0033h 1st usart 0023h timer2+exf2 002bh
m psd323x 44/176 power-saving mode two software selectable modes of reduced power consumption are implemented. idle mode the following functions are switched off. cpu (halted) the following function remain active during idle mode. external interrupts timer0, timer1, timer2 ddc interface pwm units usb interface usart 8-bit adc i 2 c interface note: interrupt or reset terminates the idle mode. power-down mode system clock halted lvd logic remains active sram contents remains unchanged the sfrs retain their value until a reset is as- serted note: the only way to exit power-down mode is a reset. table 25. power-saving mode power consumption power control register the idle and power-down modes are activated by software via the pcon register. table 26. pin status during idle and power-down mode table 27. description of the pcon bits note: 1. see the t2con register for details of the flag description mode addr/data ports1,3,4 pwm i 2 c ddc usb idle maintain data maintain data active active active active power-down maintain data maintain data disable disable disable disable sfr addr reg name bit register name reset value comments 7 654 321 0 87 pcon smod smod1 lvren adsfint rclk1 tclk1 pd idle 00 power ctrl bit symbol function 7 smod double baud data rate bit uart 6 smod1 double baud data rate bit 2nd uart 5 lvren lvr disable bit (active high) 4 adsfint enable adc interrupt 3 rclk1 1 received clock flag (uart 2) 2 tclk1 1 transmit clock flag (uart 2) 1 pd activate power-down mode (high enable) 0 idl activate idle mode (high enable)
45/176 m psd323x idle mode the instruction that sets pcon.0 is the last in- struction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. there are three ways to terminate the idle mode. n activation of any enabled interrupt will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic '1' to pcon.0. n external hardware reset: the hardware reset is required to be active for two machine cycle to complete the reset operation. n internal reset: the microcontroller restarts after 3 machine cycles in all cases. power-down mode the instruction that sets pcon.1 is the last exe- cuted prior to going into the power-down mode. once in power-down mode, the oscillator is stopped. the contents of the on-chip ram and the special function register are preserved. the power-down mode can be terminated by an external reset.
m psd323x 46/176 i/o ports (mcu module) the mcu module has five ports: port0, port1, port2, port3 and port 4. (refer to the psd module section on i/o ports a,b,c and d). ports p0 and p2 are dedicated for the external address and data bus and is not available in the 80 pin package de- vices. port1 - port3 are the same as in the standard 8032 micro-controllers, with the exception of the addi- tional special peripheral functions. all ports are bi- directional. pins of which the alternative function is not used may be used as normal bi-directional i/o. the use of port1- port4 pins as alternative func- tions are carried out automatically by the m psd323x devices provided the associated sfr bit is set high. the following sfr registers (tables 29, 30, and 31) are used to control the mapping of alternate functions onto the i/o port bits. port 1 alternate functions are controlled using the p1sfs register, except for timer 2 and the 2nd uart which are enabled by their configuration registers. p1.0 to p1.3 are default to gpio after reset. port 3 pins 6 and 7 have been modified from the standard 8032. these pins that were used for read and write control signals are now gpio or i 2 c bus pins. the read and write pins are assigned to dedicated pins. port 3 and port 4 alternate functions are controlled using the p3sfs and p4sfs special function se- lection registers. after a reset, the i/o pins default to gpio. the alternate function is enabled if the corresponding bit in the pxsfs register is set to '1.' table 28. i/o port functions table 29. p1sfs (91h) table 30. p3sfs (93h) table 31. p4sfs (94h) port name main function alternate port 1 gpio timer 2 - bits 0,1 2nd uart - bits 2,3 adc - bits 4..7 port 3 gpio uart - bits 0,1 interrupt - bits 2,3 timers - bits 4,5 i 2 c - bits 6,7 port 4 gpio ddc - bits 0..2 pwm - bits 3..7 usb +/- usb +/- only 76543210 0=port 1.7 1=ach3 0=port 1.6 1=ach2 0=port 1.5 1=ach1 0=port 1.4 1=ach0 bits reserved bits reserved 76543210 0 = port 1.7 1 = scl from i 2 cunit 0 = port 1.6 1 = sda from i 2 c unit bits are reserved. 76543210 0=port 4.7 1=pwm 4 0=port 4.6 1=pwm 3 0=port 4.5 1=pwm 2 0=port 4.4 1=pwm 1 0=port 4.3 1=pwm 0 0=port 4.2 1=v sync 0=port 4.1 1=ddc - scl 0=port 4.0 1=ddc - sda
47/176 m psd323x port type and description figure 17. port type and description (part 1) ai06653 symbol circuit description in / out reset i ? schmitt input with internal pull-up cmos compatible interface nfc : 400ns wr, rd,ale, psen o output only sink current : 5ma . xtal1, xtal2 i o on-chip oscillator on-chip feedback resistor stop in the power down mode external clock input available cmos compatible interface port0 i/o bidirectional i/o port schmitt input open-drain output(5v) address output ( push-pull ) sink current : 5ma cmos compatible interface source current: 5ma nfc xon
m psd323x 48/176 figure 18. port type and description (part 2) ai06654 symbol circuit function in/ out port1 <3:0>, port3, port4<7:3,1:0> port2 i/o port4.2 bidirectional i/o port with internal pull-ups schmitt input sink current : 5ma cmos compatible interface source current =5ma when push-pull output mode. bidirectional i/o port with internal pull-ups schmitt input. sink current : 5ma ttl compatible interface pull-up when reset address latch enable program strobe enable source current =5ma port1 < 7:4 > i/o bidirectional i/o port with internal pull-ups schmitt input sink current : 5ma cmos compatible interface analog input option source current =5ma i/o an_enb usb - , usb + bidirectional i/o port schmitt input ttl compatible interface i/o + -
49/176 m psd323x oscillator the oscillator circuit of the m psd323x devices is a single stage inverting amplifier in a pierce oscil- lator configuration. the circuitry between xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output. to drive the m psd323x devices ex- ternally, xtal1 is driven from an external source and xtal2 left open-circuit. figure 19. oscillator supervisory there are four ways to invoke a reset and initialize the m psd323x devices. n via the external reset pin n via the internal lvr block. n via usb bus reset signaling. n via watch dog timer the reset mechanism is illustrated in figure 20. figure 20. reset configuration ai06620 xtal1 xtal2 8 to 40 mhz xtal1 xtal2 external clock ai06621 reset cpu & peri. noise cancel lvr s q r cpu clock sync 10ms timer usb reset rste wdt psd_rst a active low 10ms at 40mhz 50ms at 8mhz
m psd323x 50/176 each reset source will cause an internal reset signal active. the cpu responds by executing an internal reset and puts the internal registers in a defined state. this internal reset is also routed as an active low reset input to the psd module. external reset the reset pin is connected to a schmitt trigger for noise reduction. a reset is accomplished by holding the reset pin low for at least 1ms at power up while the oscillator is running. refer to ac spec on other reset timing requirements. low v dd voltage reset an internal reset is generated by the lvr circuit when the v dd drops below the reset threshold. af- ter v dd reaching back up to the reset threshold, the reset signal will remain asserted for 10ms before it is released. on initial power-up the lvr is enabled (default). after power-up the lvr can be disabled via the lvren bit in the pcon reg- ister. note: the lvr logic is still functional in both the idle and power-down modes. the reset threshold: n 5v operation: 4v +/- 0.25v n 3.3v operation: 2.5v +/-0.2v this logic supports approximately 0.1v of hystere- sis and 1 m s noise-cancelling delay. watchdog timer overflow the watchdog timer generates an internal reset when its 22-bit counter overflows. see watchdog timer section for details. usb reset the usb reset is generated by a detection on the usb bus reset signal. a single-end zero on its upstream port for 4 to 8 times will set rstf bit in uista register. if bit 6 (rste) of the uien regis- ter is set, the detection will also generate the reset signal to reset the cpu and other periph- erals in the mcu.
51/176 m psd323x watchdog timer the hardware watchdog timer (wdt) resets the m psd323x devices when it overflows. the wdt is intended as a recovery method in situations where the cpu may be subjected to a software upset. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware/software malfunc- tion, the software will fail to reload the timer. this failure will result in a reset upon overflow thus pre- venting the processor running out of control. in the idle mode the watchdog timer and reset cir- cuitry remain active. the wdt consists of a 22-bit counter, the watchdog timer reset (wdrst) sfr and watchdog key register (wdkey). since the wdt is automatically enabled while the processor is running. the user only needs to be concerned with servicing it. the 22-bit counter overflows when it reaches 4194304 (3fffffh). the wdt increments once every machine cycle. this means the user must reset the wdt at least every 4194304 machine cycles (1.258 seconds at 40mhz). to reset the wdt the user must write a value between 00-7eh to the wdrst register. the value that is written to the wdrst is loaded to the 7msb of the 22-bit counter. this allows the user to pre-loaded the counter to an initial value to generate a flexible watchdog time out period. writing a a00o to wdrst clears the counter. the watchdog timer is controlled by the watchdog key register, wdkey. only pattern 01010101 (=55h), disables the watchdog timer. the rest of pattern combinations will keep the watchdog timer enabled. this security key will prevent the watch- dog timer from being terminated abnormally when the function of the watchdog timer is needed. in idle mode, the oscillator continues to run. to prevent the wdt from resetting the processor while in idle, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. table 32. watchdog timer key register (wdkey: 0aeh) table 33. description of the wdkey bits 76543210 wdkey7 wdkey6 wdkey5 wdkey4 wdkey3 wdkey2 wdkey1 wdkey0 bit symbol function 7to0 wdkey7 to wdkey0 enable or disable watchdog timer. 01010101 (=55h): disable watchdog timer. others: enable watchdog timer
m psd323x 52/176 watchdog reset pulse width depends on the clock frequency. the reset period is tfosc x 12 x 2 22 the reset pulse width is tfosc x 12 x 2 15 . figure 21. reset pulse width table 34. watchdog timer clear register (wdrst: 0a6h) table 35. description of the wdrst bits note: the watchdog timer (wdt) is enabled at power-up or reset and must be served or disabled. 76543210 reserved wdrst6 wdrst5 wdrst4 wdrst3 wdrst2 wdrst1 wdrst0 bit symbol function 7 e reserved 6to0 wdrst6 to wdrst0 to reset watchdog timer, write any value beteen 00h and 7eh to this register. this value is loaded to the 7 most significant bits of the 22-bit counter. for example: mov wdrst,#1eh reset period (1.258 second at 40mhz) (about 6.291 seconds at 8mhz) reset pulse width (about 10ms at 40mhz, about 50ms at 8mhz) ai06823
53/176 m psd323x timer/counters (timer0, timer1 and timer2) the m psd323x devices has three 16-bit timer/ counter registers: timer 0, timer 1 and timer2. all of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. in the atimero function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 6 cpu clock periods, the count rate is 1/6 of the cpu clock frequency. in the acountero function, the register is increment- ed in response to a 1-to-0 transition at its corre- sponding external input pin, t0 or t1. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cy- cle, the count is incremented. the new count value appears in the register during s2p1 of the cycle following the one in which the transition was de- tected. since it takes 2 machine cycles (12 cpu clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the cpu clock fre- quency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full cy- cle. in addition to the atimero or acountero selec- tion, timer0 and timer1 have four operating modes from which to select. timer0 and timer1 the atimero or acountero function is selected by control bits c/ t in the special function register tmod. these timer/counters have four operat- ing modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for timers/ counters. mode 3 is different. the four op- erating modes are de-scribed in the following text. table 36. control register (tcon) table 37. description of the tcon bits 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function 7tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on or off 5tf0 timer 0 overflow flag. set by hardier on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on or off 3ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed 2it1 interrupt 1 type control bit. set/cleared by software to specify falling-edge/low-level triggered external interrupt 1ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed 0it0 interrupt 0 type control bit. set/cleared by software to specify falling-edge/low-level triggered external interrupt
m psd323x 54/176 mode 0. putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 22 shows the mode 0 operation as it applies to timer1. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all '1s' to all '0s,' it sets the timer interrupt flag tf1. the counted input is enabled to the timer when tr1 = 1 and either gate = 0 or /int1 = 1. (setting gate = 1 allows the timer to be controlled by external in- put /int1, to facilitate pulse width measurements). tr1 is a control bit in the special function regis- ter tcon (tcon control register). gate is in tmod. the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl1. the upper 3 bits of tl1 are indeterminate and should be ignored. setting the run flag does not clear the registers. mode 0 operation is the same for the timer0 as for timer1. substitute tr0, tf0, and /int0 for the corresponding timer1 signals in figure 22. there are two different gate bits, one for timer1 and one for timer0. mode 1. mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. table 38. tmod register (tmod) table 39. description of the tmod bits 76543210 gate c/t m1 m0 gate c/t m1 m0 bit symbol timer function 7 gate timer1 gating control when set. timer/counter 1 is enabled only while int1 pin is high and tr1 control pin is set. when cleared, timer 1 is enabled whenever tr1 control bit is set 6 c/t timer or counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from t1 input pin) 5 m1 (m1,m0)=(0,0): 13-bit timer/counter, th1, with tl1 as 5-bit prescaler (m1,m0)=(0,1): 16-bit timer/counter. th1 and tl1 are cascaded. there is no prescaler. (m1,m0)=(1,0): 8-bit auto-reload timer/counter. th1 holds a value which is to be reloaded into tl1 each time it overflows (m1,m0)=(1,1): timer/counter 1 stopped 4m0 3 gate timer0 gating control when set. timer/counter 0 is enabled only while int0 pin is high and tr0 control pin is set. when cleared, timer 0 is enabled whenever tr0 control bit is set 2 c/t timer or counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from t0 input pin) 1 m1 (m1,m0)=(0,0): 13-bit timer/counter, th0, with tl0 as 5-bit prescaler (m1,m0)=(0,1): 16-bit timer/counter. th0 and tl0 are cascaded. there is no prescaler. (m1,m0)=(1,0): 8-bit auto-reload timer/counter. th0 holds a value which is to be reloaded into tl0 each time it overflows (m1,m0)=(1,1): tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits 0m0
55/176 m psd323x figure 22. timer/counter mode 0: 13-bit counter figure 23. timer/counter mode 2: 8-bit auto-reload ai06622 f osc tf1 interrupt gate tr1 int1 pin t1 pin control tl1 (5 bits) th1 (8 bits) c/t = 0 c/t = 1 12 ai06623 f osc tf1 interrupt gate tr1 int1 pin t1 pin control tl1 (8 bits) th1 (8 bits) c/t = 0 c/t = 1 12
m psd323x 56/176 figure 24. timer/counter mode 3: two 8-bit counters mode 2. mode 2 configures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in figure 23. overflow from tl1 not only sets tf1, but also reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 2 operation is the same for timer/counter 0. mode 3. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 24. tl0 uses the timer 0 con- trol bits: c/t, gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cy- cles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1a in- terrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an m psd323x devices can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. timer 2 like timer 0 and 1, timer 2 can operate as either an event timer or as an event counter. this is select- ed by bit c/t2 in the special function register t2con. it has three operating modes: capture, autoload, and baud rate generator, which are se- lected by bits in the t2con as shown in table 41. in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter which upon overflowing sets bit tf2, the timer 2 over- flow bit, which can be used to generate an inter- rupt. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the cur- rent value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt. the cap- ture mode is illustrated in figure 25. in the auto-reload mode, there are again two op- tions, which are selected by bit exen2 in t2con. if exen2 = 0, then when timer 2 rolls over it not only sets tf2 but also causes the timer 2 regis- ters to be reloaded with the 16-bit value in regis- ters rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2. the auto-reload mode is illustrated in standard serial interface (uart) figure 26. the baud rate generation mode is selected by (rclk, rclk1)=1 and/or (tclk, tclk1)=1. it will be described in conjunc- tion with the serial port. ai06624 f osc tf0 interrupt gate tr0 int0 pin t0 pin control tl0 (8 bits) c/t = 0 c/t = 1 12 f osc tf1 interrupt control th1 (8 bits) 12 tr1
57/176 m psd323x table 40. timer/counter 2 control register (t2con) table 41. description of the t2con bits note: 1. the rclk1 and tclk1 bits in the pcon register control uart 2, and have the same function as rclk and tclk. 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 bit symbol function 7tf2 timer 2 overflow flag. set by a timer 2 overflow, and must be cleared by software. tf2 will not be set when either (rclk, rclk1)=1 or (tclk, tclk)=1 6exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2=1. when timer 2 interrupt is enabled, exf2=1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software 5 rclk 1 receive clock flag (uart 1). when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. tclk=0 causes timer 1 overflow to be used for the receive clock 4 tclk 1 transmit clock flag (uart 1). when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk=0 causes timer 1 overflow to be used for the transmit clock 3 exen2 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2=0 causes time 2 to ignore events at t2ex 2 tr2 start/stop control for timer 2. a logic 1 starts the timer 1 c/t2 timer or counter select for timer 2. cleared for timer operation (input from internal system clock, t cpu ); set for external event counter operation (negative edge triggered) 0 cp/rl2 capture/reload flag. when set, capture will occur on negative transition of t2ex if exen2=1. when cleared, auto-reload will occur either with timer 2 overflows, or negative transitions of t2ex when exen2=1. when either (rclk, rclk1)=1 or (tclk, tclk)=1, this bit is ignored, and timer is forced to auto-reload on timer 2 overflow
m psd323x 58/176 table 42. timer/counter2 operating modes note: = falling edge figure 25. timer 2 in capture mode mode t2con t2mod decn t2con exen p1.1 t2ex remarks inpu t clock rxclk or txclk cp/ rl2 tr2 internal external (p1.0/t2) 16-bit auto- reload 0 0 1 0 0 x reload upon overflow f osc /12 max f osc /24 0010 1 reload trigger (falling edge) 0 0 1 1 x 0 down counting 0 0 1 1 x 1 up counting 16-bit capture 011x 0x 16-bit timer/counter (only up counting) f osc /12 max f osc /24 011x 1 capture (th1,tl2) (rcap2h,rcap2l) baud rate generator 1x1x 0x no overflow interrupt request (tf2) f osc /12 max f osc /24 1x1x 1 extra external interrupt (timer 2) off x x 0 x x x timer 2 stops e e ai06625 f osc tf2 capture tr2 t2 pin control tl2 (8 bits) th2 (8 bits) c/t2 = 0 c/t2 = 1 12 exp2 control exen2 rcap2l rcap2h t2ex pin timer 2 interrupt transition detector
59/176 m psd323x figure 26. timer 2 in auto-reload mode ai06626 f osc tf2 reload tr2 t2 pin control tl2 (8 bits) th2 (8 bits) c/t2 = 0 c/t2 = 1 12 exp2 control exen2 rcap2l rcap2h t2ex pin timer 2 interrupt transition detector
m psd323x 60/176 standard serial interface (uart) the m psd323x devices provides two standard 8032 uart serial ports. the first port is connected to pin p3.0 (rx) and p3.1 (tx). the second port is connected to pin p1.2 (rx) and p1.3(tx). the op- eration of the two serial ports are the same and are controlled by the scon and scon2 registers. the serial port is full duplex, meaning it can trans- mit and receive simultaneously. it is also receive- buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf (or sbuf2 for the second serial port). writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0. serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are trans- mitted/received (lsb first). the baud rate is fixed at 1/6 the cpu clock frequency. mode 1. 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2. 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of '0' or '1.' or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is pro- grammable to either 1/32 or 1/64 the oscillator fre- quency. mode 3. 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination regis- ter. reception is initiated in mode 0 by the condi- tion ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multi- processor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be pro- grammed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multi-proces- sor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is '1' in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupt- ed by a data byte. an ad-dress byte, however, will interrupt all slaves, so that each slave can exam- ine the received byte and see if it is being ad- dressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being ad- dressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is re- ceived. serial port control register the serial port control and status register is the special function register scon (scon2 for the second port), shown in figure 27. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). table 43. serial port control register (scon) 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri
61/176 m psd323x table 44. description of the scon bits bit symbol function 7 sm0 (sm1,sm0)=(0,0): shift register. baud rate = f osc /12 (sm1,sm0)=(1,0): 8-bit uart. baud rate = variable (sm1,sm0)=(0,1): 8-bit uart. baud rate = f osc /64 or f osc /32 (sm1,sm0)=(1,1): 8-bit uart. baud rate = variable 6 sm1 5 sm2 enables the multiprocessor communication features in mode 2 and 3. in mode 2 or 3, if sm2 is set to '1,' r1 will not be activated if its received 8th data bit (rb8) is '0.' in mode 1, if sm2=1, r1 will not be activated if a valid stop bit was not received. in mode 0, sm2 should be '0' 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception 3tb8 the 8th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired 2rb8 in modes 2 and 3, this bit contains the 8th data bit that was received. in mode 1, if sm2=0, rb8 is the snap bit that was received. in mode 0, rb8 is not used 1ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software 0ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit in the other modes, in any serial reception (except for sm2). must be cleared by software
m psd323x 62/176 baud rates. the baud rate in mode 0 is fixed: mode 0 baud rate = fosc / 12 the baud rate in mode 2 depends on the value of bit smod = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. mode 2 baud rate = (2 smod / 64) x fosc in the m psd323x devices, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. using timer 1 to generate baud rates. when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows (see: mode 1,3 baud rate = (2 smod / 32) x (timer 1 overflow rate) the timer 1 interrupt should be disabled in this ap- plication. the timer itself can be configured for ei- ther atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-re- load mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1,3 baud rate = = (2 smod / 32) x (fosc / 12 x [256 - (th1)] one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and con- figuring the timer to run as a 16-bit timer (high nib- ble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 22 lists various commonly used baud rates and how they can be obtained from timer 1. using timer/counter 2 to generate baud rates. in the m psd323x devices, timer 2 select- ed as the baud rate generator by setting tclk and/or rclk (see figure 22, page 55 timer/ counter 2 control register (t2con)). note: the baud rate for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer into its baud rate generator mode. the rclk and tclk bits in the t2con register configure uart 1. the rclk1 and tclk1 bits in the pcon register configure uart 2. the baud rate generator mode is similar to the auto-reload mode, in that a roll over in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. now, the baud rates in modes 1 and 3 are deter- mined at timer 2's overflow rate as follows: mode 1,3 baud rate = timer 2 overflow rate / 16 table 45. timer 1-generated commonly used baud rates baud rate f osc smod timer 1 c/t mode reload value mode 0 max: 1mhz 12mhz xxxx mode 2 max: 375k 12mhz 1 x x x modes 1, 3: 62.5k 12mhz 1 0 2 ffh 19.2k 11.059mhz 1 0 2 fdh 9.6k 11.059mhz 0 0 2 fdh 4.8k 11.059mhz 0 0 2 fah 2.4k 11.059mhz 0 0 2 f4h 1.2k 11.059mhz 0 0 2 e8h 137.5 11.059mhz 0 0 2 1dh 110 6mhz 0 0 2 72h 110 12mhz 0 0 1 feebh
63/176 m psd323x the timer can be configured for either atimero or acountero operation. in the most typical applica- tions, it is configured for atimero operation (c/t2 = 0). atimero operation is a little different for timer 2 when it's being used as a baud rate generator. normally, as a timer it would increment every ma- chine cycle (thus at the 1/6 the cpu clock frequen- cy). in the case, the baud rate is given by the formula: mode 1,3 baud rate = fosc / (32 x [65536 - (rcap2h, rcap2l)] where (rcap2h, rcap2l) is the content of rc2h and rc2l taken as a 16-bit unsigned inte- ger. timer 2 also be used as the baud rate generating mode. this mode is valid only if rclk + tclk = 1 in t2con or in pcon. note: a roll-over in th2 does not set tf2, and will not generate an interrupt. therefore, the timer in- terrupt does not have to be disabled when timer 2 is in the baud rate generator mode. note: if exen2 is set, a 1-to-0 transition in t2ex will set exf2 but will not cause a reload from (rcap2h, rcap2l) to (th2, tl2). thus when timer 2 is in use as a baud rate generator, t2ex can be used as an extra external interrupt, if de- sired. it should be noted that when timer 2 is running (tr2 = 1) in atimero function in the baud rate gen- erator mode, one should not try to read or write th2 or tl2. under these conditions the timer is being incremented every state time, and the results of a read or write may not be accu- rate. the rc registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. turn the timer off (clear tr2) before accessing the timer 2 or rc registers, in this case. more about mode 0. serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed a 1/6 the cpu clock frequency. figure 27, page 65 shows a simplified functional diagram of the serial port in mode 0, and associat- ed timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a '1' into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate out-put function line of rxd and also en- able shift clock to the alternate output func- tion line of txd. shift clock is low during s3, s4, and s5 of every machine cycle, and high dur- ing s6, s1, and s2. at s6p2 of every machine cy- cle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deacti- vate send and set t1. both of these actions occur at s1p1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enables shift clock to the alternate output function line of txd. shift clock makes transitions at s3p1 and s6p1 of every machine cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the rxd pin at s5p2 of the same machine cycle. as data bits come in from the right, '1s' shift out to the left. when the '0' that was initially loaded into the right-most position arrives at the left-most po- sition in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1. ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first). and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the m psd323x devices the baud rate is deter- mined by the timer 1 over-flow rate. figure 29 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a '1' into the 9th bit po- sition of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the di- vide-by-16 counter. (thus, the bit times are syn- chronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of
m psd323x 64/176 the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deac- tivate send and set ti. this occurs at the 10th di- vide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transi- tion at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been es- tablished. when a transition is detected, the di- vide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an-other 1-to- 0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the re- set of the rest of the frame will proceed. as data bits come in from the right, '1s' shift out to the left. when the start bit arrives at the left-most position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generat- ed: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the re- ceived frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3. eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a pro- grammable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of '0' or '1.' on receive, the data bit goes into rb8 in scon. the baud rate is programma- ble to either 1/16 or 1/32 the cpu clock frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1. figure 31, page 67 and figure 33, page 68 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit po- sition of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next roll-over in the divide-by- 16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a '1' (the stop bit) into the 9th bit position of the shift register. there-after, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the out-put position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then de- activate send and set ti. this occurs at the 11th divide-by 16 rollover after awrite to subf.o reception is initiated by a detected 1-to-0 transi- tion at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been es- tablished. when a transition is detected, the di- vide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an- other 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and recep- tion of the rest of the frame will proceed. as data bits come in from the right, '1s' shift out to the left. when the start bit arrives at the left-most position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following con- ditions are met at the time the final shift pulse is generated:
65/176 m psd323x 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1 if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input. figure 27. serial port mode 0, block diagram ai06824 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift shift clock serial port interrupt s6 ren r1 rx clock start tx clock start shift shift send receive t r cl ds q 76543210 rxd p3.0 alt input function rxd p3.0 alt output function txd p3.1 alt output function
m psd323x 66/176 figure 28. serial port mode 0, waveforms figure 29. serial port mode 1, block diagram ai06825 write to sbuf send shift rxd (data out) txd (shift clock) t write to scon ri receive shift rxd (data in) txd (shift clock) s6p2 s3p1 s6p1 clear ri receive transmit d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ai06826 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 timer1 overflow timer2 overflow 0 01 1 01 tclk rclk smod
67/176 m psd323x figure 30. serial port mode 1, waveforms figure 31. serial port mode 2, block diagram ai06843 write to sbuf data shift txd t1 rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit tb8 d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit rb8 ai06844 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 phase2 clock 1/2*f osc 01 smod
m psd323x 68/176 figure 32. serial port mode 2, waveforms figure 33. serial port mode 3, block diagram ai06845 write to sbuf data shift txd ti rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit tb8 d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit rb8 stop bit generator ai06846 zero detector internal bus tx control rx control internal bus sbuf write to sbuf read sbuf load sbuf sbuf input shift register shift serial port interrupt rx clock start tx clock start shift shift send load sbuf ti ri cl ds q 1ffh txd data rx detector rxd 1-to-0 transition detector 16 sample 16 2 tb8 timer1 overflow timer2 overflow 0 01 1 01 tclk rclk smod
69/176 m psd323x figure 34. serial port mode 3, waveforms ai06847 write to sbuf data shift txd ti rx clock rxd bit detector sample times shift ri s1p1 16 reset receive transmit d0 d1 d2 d3 d4 d5 d6 d7 send tx clock start bit stop bit tb8 d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit rb8 stop bit generator
m psd323x 70/176 analog-to-digital convertor (adc) the analog to digital (a/d) converter allows con- version of an analog input to a corresponding 8-bit digital value. the a/d module has four analog in- puts, which are multiplexed into one sample and hold. the output of the sample and hold is the in- put into the converter, which generates the result via successive approximation. the analog supply voltage is connected to avref of ladder resis- tance of a/d module. the a/d module has two registers which are the control register acon and a/d result register adat. the register acon, shown in table 47, page 71, controls the operation of the a/d convert- er module. to use analog inputs, i/o is selected by p1sfs register. also an 8-bit prescaler ascl di- vides the main system clock input down to approx- imately 6mhz clock that is required for the adc logic. appropriate values need to be loaded into the prescaler based upon the main mcu clock fre- quency prior to use. the processing of conversion starts when the start bit adst is set to '1.' after one cycle, it is cleared by hardware. the register adat contains the results of the a/d conversion. when conver- sion is completed, the result is loaded into the adat the a/d conversion status bit adsf is set to '1.' the block diagram of the a/d module is shown in figure 35. the a/d status bit adsf is set auto- matically when a/d conversion is completed, cleared when a/d conversion is in process. the ascl should be loaded with a value that re- sults in a clock rate of approximately 6mhz for the adc using the following formula: adc clock input = (fosc / 2) / (prescaler register value +1) where fosc is the mcu clock input frequency the conversion time for the adc can be calculat- ed as follows: adc conversion time = 8 clock * 8bits * (adc clock) ~= 10.67usec (at 6mhz) adc interrupt the adsf bit in the acon register is set to '1' when the a/d conversion is complete. the status bit can be driven by the mcu, or it can be config- ured to generate a falling edge interrupt when the conversion is complete. the adsf interrupt is enabled by setting the ads- fint bit in the pcon register. once the bit is set, the external int1 interrupt is disabled and the adsf interrupt takes over as int1. int1 must be configured as if it is an edge interrupt input. the inp1 pin (p3.3) is available for general i/o func- tions, or timer1 gate control. figure 35. a/d block diagram ai06627 input mux ach0 ach1 ach2 ach3 acon internal bus adat avref ladder resistor d ecode s/h successive approximation circuit conversion complete interrupt
71/176 m psd323x table 46. adc sfr memory map table 47. description of the acon bits table 48. adc clock input sfr addr reg name bit register name reset value comments 7 654 321 0 95 ascl 00 8-bit prescaler for adc clock 96 adat adat7 adat6 adat5 adat4 adat3 adat2 adat1 adat0 00 adc data register 97 acon aden ads1 ads0 adst adsf 00 adc control register bit symbol function 7 to 6 e reserved 5 aden adc enable bit: 0 : adc shut off and consumes no operating current 1 : enable adc 4 e reserved 3to2 ads1, ads0 analog channel select 0, 0 channel0 (ach0) 0, 1 channel1 (ach1) 1, 0 channel2 (ach2) 1, 1 channel3 (ach3) 1 adst adc start bit: 0 : force to zero 1 : start an adc; after one cycle, bit is cleared to '0' 0 adsf adc status bit: 0 : a/d conversion is in process 1 : a/d conversion is completed, not in process mcu clock frequency prescaler register value adc clock 40mhz 2 6.7mhz 36mhz 2 6mhz 24mhz 1 6mhz 12mhz 0 6mhz
m psd323x 72/176 pulse width modulation (pwm) the pwm block has the following features: n four-channel, 8-bit pwm unit with 16-bit prescaler n one-channel, 8-bit unit with programmable frequency and pulse width n pwm output with programmable polarity 4-channel pwm unit (pwm 0-3) the 8-bit counter of a pwm counts module 256 (i.e., from 0 to 255, inclusive). the value held in the 8-bit counter is compared to the contents of the special function register (pwm 0-3) of the corre- sponding pwm. the polarity of the pwm outputs is programmable and selected by the pwml bit in pwmcon register. provided the contents of a pwm 0-3 register is greater than the counter val- ue, the corresponding pwm output is set high (with pwml = 0). when the contents of this regis- ter is less than or equal to the counter value, the corresponding pwm output is set low (with pwml = 0). the pulse-width-ratio is therefore de- fined by the contents of the corresponding special function register (pwm 0-3) of a pwm. by load- ing the corresponding special function register (pwm 0-3) with either 00h or ffh, the pwm out- put can be retained at a constant high or low level respectively (with pwml = 0). for each pwm unit, there is a 16-bit prescaler that are used to divide the main system clock to form the input clock for the corresponding pwm unit. this prescaler is used to define the desired repeti- tion rate for the pwm unit. sfr registers b1h - b2h are used to hold the 16-bit divisor values. the repetition frequency of the pwm output is giv- en by: fpwm 8 =(f osc / prescaler0) / (2 x 256) and the input clock frequency to the pwm counters is = f osc / 2 / (prescaler data value + 1) see the i/o ports (mcu module), page 46 for more information on how to configure the port 4 pin as pwm output.
73/176 m psd323x figure 36. four-channel 8-bit pwm block diagram ai06647 8-bit pwm0-pwm3 comparators registers 8-bit pwm0-pwm3 comparators 8 8 8-bit counter x4 8-bit pwm0-pwm3 data registers 8 x4 port4.3 port4.4 port4.5 port4.6 overflow clock load 16-bit prescaler register (b2h,b1h) 16 16-bit prescaler counter f osc /2 cpu rd/wr cpu rd/wr load pwmcon bit5 (pwme) pwmcon bit7 (pwml) 4 8 data bus x4 8 8
m psd323x 74/176 table 49. pwm sfr memory map pwmcon register bit definition: pwml = pwm 0-3 polarity control pwmp = pwm 4 polarity control pwme = pwm enable (0 = disabled, 1= enabled) cfg3..cfg0 = pwm 0-3 output (0 = open drain; 1 = push-pull) cfg4 = pwm 4 output (0 = open drain; 1 = push-pull) sfr addr reg name bit register name reset value comment s 76543210 a1 pwmcon pwml pwmp pwme cfg4 cfg3 cfg2 cfg1 cfg0 00 pwm control polarity a2 pwm0 00 pwm0 output duty cycle a3 pwm1 00 pwm1 output duty cycle a4 pwm2 00 pwm2 output duty cycle a5 pwm3 00 pwm3 output duty cycle aa pwm4p 00 pwm 4 period ab pwm4w 00 pwm 4 pulse width b1 pscl0l 00 prescaler 0 low (8-bit) b2 pscl0h 00 prescaler 0 high (8-bit) b3 pscl1l 00 prescaler 1 low (8-bit) b4 pscl1h 00 prescaler 1 high (8-bit)
75/176 m psd323x programmable period 8-bit pwm the pwm 4 channel can be programmed to pro- vide a pwm output with variable pulse width and period. the pwm 4 has a 16-bit prescaler, an 8- bit counter, a pulse width register, and a period register. the pulse width register defines the pwm pulse width time, while the period register defines the period of the pwm. the input clock to the prescaler is f osc /2. the pwm 4 channel is as- signed to port 4.7. figure 37. programmable pwm 4 channel block diagram ai07091 port 4.7 16-bit prescaler register (b4h, b3h) 16-bit prescaler counter 8-bit counter 8-bit pwm4p register (period) 8-bit pwm4 comparator register 8-bit pwm4 comparator pwm4 control match cpu rd/wr load load clock reset pwmcon bit 6 (pwmp) data bus cpu rd/wr f osc /2 pwmcon bit 5 (pwme) 8 16 8 8 8 8 8-bit pwm4w register (width) 8-bit pwm4 comparator register 8-bit pwm4 comparator 8 88 8 8
m psd323x 76/176 pwm 4 channel operation the 16-bit prescaler1 divides the input clock (f osc /2) to the desired frequency, the resulting clock runs the 8-bit counter of the pwm 4 chan- nel. the input clock frequency to the pwm 4 counter is: f pwm4 = (f osc /2)/(prescaler1 data value +1) when the prescaler1 register (b4h, b3h) is set to data value '0,' the maximum input clock frequency to the pwm 4 counter is f osc /2 and can be as high as 20mhz. the pwm 4 counter is a free-running, 8-bit counter. the output of the counter is compared to the compare registers, which are loaded with data from the pulse width register (pwm4w, abh) and the period register (pwm4p, aah). the pulse width register defines the pulse duration or the pulse width, while the period register defines the period of the pwm. when the pwm 4 channel is enabled, the register values are loaded into the comparator registers and are compared to the counter output. when the content of the counter is equal to or greater than the value in the pulse width register, it sets the pwm 4 output to low (with pwmp bit = 0). when the period register equals to the pwm4 counter, the counter is cleared, and the pwm 4 channel output is set to logic 'high' level (beginning of the next pwm pulse). the period register cannot have a value of a00o and its content should always be greater than the pulse width register. the prescaler1 register, pulse width register, and period register can be modified while the pwm 4 channel is active. the values of these reg- isters are automatically loaded into the prescaler counter and comparator registers when the cur- rent pwm 4 period ends. the pwmcon register (bits 5 and 6) controls the enable/disable and polarity of the pwm 4 channel. figure 38. pwm 4 with programmable pulse width and frequency ai07090 pwm4 defined by pulse width register switch level reset counter defined by period register
77/176 m psd323x i 2 c interface there are two serial i 2 c ports implemented in the m psd323x devices. the serial port supports the twin line i 2 c-bus, con- sists of a data line (sdax) and a clock line (sclx). depending on the configuration, the sda and scl lines may require pull-up resistors. n sda1, scl1: the serial port line for ddc protocol n sda2, scl2: the serial port line for general i 2 c bus connection in both i 2 c interfaces, these lines also function as i/o port lines as follows. n sda1 / p4.0, scl1 / p4.1, sda2 / p3.6, scl2 / p3.7 the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c serial i/o has complete autonomy in byte handling and operates in 4 modes. n master transmitter n master receiver n slave transmitter n slave receiver these functions are controlled by the sfrs. n sxcon: the control of byte handling and the operation of 4 mode. n sxsta: the contents of its register may also be used as a vector to various service routines. n sxdat: data shift register. n sxadr: slave address register. slave address recognition is performed by on-chip h/w. figure 39. block diagram of the i 2 c bus serial i/o ai06649 sclx sdax bus clock generator arbitration and sync. logic shift register status register 70 slave address 70 control register 70 70 internal bus
m psd323x 78/176 table 50. serial control register (sxcon: s1con, s2con) table 51. description of the sxcon bits table 52. selection of the serial clock frequency scl in master mode 76543210 cr2 enii sta sto addr aa cr1 cr0 bit symbol function 7cr2 this bit along with bits cr1and cr0 determines the serial clock frequency when sio is in the master mode. 6enii enable iic. when eni1 = 0, the iic is disabled. sda and scl outputs are in the high impedance state. 5sta start flag. when this bit is set, the sio h/w checks the status of the i 2 c-bus and generates a start condition if the bus free. if the bus is busy, the sio will generate a repeated start condition when this bit is set. 4 sto stop flag. with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i 2 c-bus, the i 2 c hardware clears the sto flag. note: this bit have to be set before 1 cycle interrupt period of stop. that is, if this bit is set, stop condition in master mode is generated after 1 cycle interrupt period. 3 addr this bit is set when address byte was received. must be cleared by software. 2aa acknowledge enable signal. if this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: ? own slave address is received ? a data byte is received while the device is programmed to be a master receiver ? a data byte is received while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. sio release sda line as high during the acknowledge clock pulse. 1cr1 these two bits along with the cr2 bit determine the serial clock frequency when sio is in the master mode. 0cr0 cr2 cr1 cr0 f osc divisor bit rate (khz) at f osc 12mhz 24mhz 36mhz 40mhz 0 0 0 16 375 750 x x 0 0 1 24 250 500 750 833 0 1 0 30 200 400 600 666 0 1 1 60 100 200 300 333 1 0 0 120 50 100 150 166 1 0 124025507583 1 1 0 480 12.5 25 37.5 41 1 1 1 960 6.25 12.5 18.75 20
79/176 m psd323x serial status register (sxsta: s1sta, s2sta) sxsta is a aread-onlyo register. the contents of this register may be used as a vector to a service routine. this optimized the response time of the software and consequently that of the i 2 c-bus. the status codes for all possible modes of the i 2 c- bus interface are given table 54. this flag is set, and an interrupt is generated, after any of the following events occur. 1. own slave address has been received during aa = 1: ack_int 2. the general call address has been received while gc(sxadr.0) = 1 and aa = 1: 3. a data byte has been received or transmitted in master mode (even if arbitration is lost): ack_int 4. a data byte has been received or transmitted as selected slave: ack_int 5. a stop condition is received as selected slave receiver or transmitter: stop_int data shift register (sxdat: s1dat, s2dat) sxdat contains the serial data to be transmitted or data which has just been received. the msb (bit 7) is transmitted or received first; that is, data shifted from right to left. table 53. serial status register (sxsta) table 54. description of the sxsta bits note: 1. interrupt flag bit (intr, sxsta bit 5) is cleared by hardware as reading sxsta register. 2. i 2 c interrupt flag (intr) can occur in below case. (except ddc2b mode at swenb= 0) table 55. data shift register (sxdat: s1dat, s2dat) 76543210 gc stop intr tx_mode bbusy blost /ack_rep slv bit symbol function 7 gc general call flag 6 stop stop flag. this bit is set when a stop condition is received 5 intr interrupt flag. this bit is set when an i c interrupt condition is requested 4 tx_mode transmission mode flag. this bit is set when the i c is a transmitter; otherwise this bit is reset 3 bbusy bus busy flag. this bit is set when the bus is being used by another master; otherwise, this bit is reset 2 blost bus lost flag. this bit is set when the master loses the bus contention; otherwise this bit is reset 1 /ack_rep acknowledge response flag. this bit is set when the receiver transmits the not acknowledge signal this bit is reset when the receiver transmits the acknowledge signal 0slv slave mode flag. this bit is set when the i c plays role in the slave mode; otherwise this bit is reset 76543210 sxdat7 sxdat6 sxdat5 sxdat4 sxdat3 sxdat2 sxdat1 sxdat0
m psd323x 80/176 address register (sxadr: s1adr, s2adr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/transmitter. the start/stop hold time detection and system clock registers (tables 57 and 58) are included in the i 2 c unit to specify the start/stop detection time to work with the large range of mcu frequency val- ues supported. for example, with a system clock of 40mhz. table 56. address register (sxadr) note: 1. sla6 to sla0: own slave address. table 57. start /stop hold time detection register (s1setup, s2setup) table 58. system cock of 40mhz table 59. system clock setup examples 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 e address register name reset value note sfr d1h s1setup 00h to control the start/stop hold time detection for the ddc module in slave mode d2h s2setup 00h to control the start/stop hold time detection for the multi-master i c module in slave mode s1setup, s2setup register value number of sample clock (f osc /2 -> 50ns) required start/ stop hold time note 00h 1ea 50ns when bit 7 (enable bit) = 0, the number of sample clock is 1ea (ignore bit 6 to bit 0) 80h 1ea 50ns 81h 2ea 100ns 82h 3ea 150ns ... ... ... 8bh 12ea 600ns fast mode i c start/stop hold time specification ... ... ... ffh 128ea 6000ns system clock s1setup, s2setup register value number of sample clock required start/stop hold time 40mhz (f osc /2 -> 50ns) 8bh 12 ea 600ns 30mhz (f osc /2 -> 66.6ns) 89h 9 ea 600ns 20mhz (f osc /2 -> 100ns) 86h 6 ea 600ns 8mhz (f osc /2 -> 250ns) 83h 3 ea 750ns
81/176 m psd323x programmer's guide for i 2 c and ddc2 the i 2 c serial i/o and ddc interface operates in four modes. n master transmitter n master receiver n slave transmitter n slave receiver master transmitter mode flow. 1. read sxsta. 2. if bbusy == 1 then go to step1. else then write slave address to sxdat and set both eni and sta, reset aa in sxcon. 3. wait for interrupt. 4. read sxsta. if blost == 1 or /ack_rep == 1* then write dummy data to sxdat. go to step1. else then clear sta. 5. perform required service routines. if this datum == last then set sto in sxcon and write last data to sx- dat**. go to step 6. else then write next data to sxdat**. go to step3. 6. wait for interrupt. write dummy data to sxdat**. note: 1. (*) if the master don't receive the acknowledge from the slave, it generates the stop condition and returns to the idle state. 2. (**) this action should be the last in service routine. slave transmitter mode flow. 1. write slave address to sxadr, set aa and eni in sxcon. 2. wait for interrupt. 3. read sxsta and write the first data to sxdat*. reset aa in sxcon. 4. wait for interrupt. 5. read sxsta. if /ack_rep == 1** then go to step7. else then write the next sxdat*. go to step5. 6. write dummy data to sxdat*. note: 1. (*) these actions should be the last. 2. (**) if the master want to stop the current data requests, it don't have to acknowledge to the slave transmitter. 3. if the slave does not receive the acknowledge from the master, it releases the sda and enters the idle state, so if the master is to resume the data requests, it must re- generate the start condition.
m psd323x 82/176 master receiver mode flow. 1. read sxsta. 2. if bbusy == 1 then go to step1. else then write slave address to sxdat and set both eni1 and sta, reset aa in sxcon. 3. wait for interrupt. 4. read sxsta. if blost == 1 or /ack_rep == 1 then write dummy data to sxdat go to step1. else then clear sta and write ffh to sxdat. set aa in sxcon. 5. wait for interrupt. 6. read sxsta. if this datum == last then reset aa* and read sxdat**. go to step7. else then read sxdat**. go to step5. 7. wait for interrupt. read sxsta. read sxdat**. note: 1. (*) if the master want to terminate the current data re- quests, it don't have to acknowledge to the slave. 2. (**) this action should be the last. slave transmitter mode. 1. write slave address to sxadr, set aa and eni in sxcon. 2. wait for interrupt. 3. read sxsta and write ffh to sxdat*. 4. 5. wait for interrupt. 6. read sxsta. if stop == 1 then go to step7. else then read data from sxdat*. go to step5. 7. read dummy data from sxdat*. note: 1. (*) this action should be the last.
83/176 m psd323x ddc interface the basic ddc unit consists of an i 2 c interface and 256 bytes of sram for ddc data storage. the 8032 core is responsible of loading the contents of the sram with the ddc data. the ddc unit has the following features: n supports both ddc1 and ddc2b modes. n features 256 bytes of ddc data - initialized by the 8032 n supports fully automatic operation of ddc1 and ddc2b modes n ddc operates in slave mode only. n sw interrupt mode available (existing design) the interface signals for the ddc can be mapped to pins in port 4. the interface consists of the stan- dard v sync (p4.2), sda (p4.0) and scl (p4.1) ddc signals. the conceptual block diagram is il- lustrated in figure 43. figure 40. ddc interface block diagram ai06628 int ddccon intr (from sista) initialization synchronization ddcadr address pointer ram buffer rambuf vsync en ddc1 transmitter ddcdat ddc1 hold register ddc1/ddc2 detection sista sicon scl1 sda1 bus clock generator arbitration logic s1dat s1adr1 s1adr0 shift register ddc2b/ddc2ab ddc2b+interface internal bus monitor address monitor address 10 xx ex_ dat sw enb ddc1 int ddc1 en swh int m0
m psd323x 84/176 special function register for the ddc interface there are eight sfr in the ddc interface: rambuf, ddccon, ddcadr, ddcdat are ddc registers. s1con, s1sta, s1dat, s1adr are i 2 c inter- face registers, same as the ones described in the standalone i 2 c bus. ddcdat register. ddc1 data register for transmission (ddcdat: 0d5h) n 8-bit read and write register. n indicates data byte to be transmitted in ddc1 protocol. ddcadr register. address pointer for ddc in- terface (ddcadr: 0d6h) n 8-bit read and write register. n address pointer with the capability of the post increment. after each access to rambuf register (either by software or by hardware ddc1 interface), the content of this register will be increased by one. it's available both in ddc1, ddc2 (ddc2b, ddc2b+, and ddc2ab) and system operation. table 60. ddc sfr memory map sfr addr reg name bit register name reset value comments 76543210 d4 rambuf xx ddc ram buffer d5 ddcdat 00 ddc data xmit register d6 ddcadr 00 addr pointer register d7 ddccon e ex_dat swenb ddc_ax ddcint ddc1en swhint m0 00 ddc control register
85/176 m psd323x table 61. description of the ddcon register bits bit symbol function 7 e reserved 6 ex_dat 0 = the sram has 128 bytes (default) 1 = the sram has 256 bytes 5 swenb note: this bit is valid for ddc1 & ddc2b modes 0 = data is automatically read from sram at the current location of ddcadr and sent out via current ddc protocol. (default) 1 = mcu is interrupted during the current data byte transmission period to load the next byte of data to send out. 4 ddc_ax note: this bit is valid for ddc1 & ddc2b modes 0 = data is automatically read from sram at the current location of ddcadr and sent out via current ddc protocol. (default) 1 = mcu is interrupted during the current data byte transmission period to load the next byte of data to send out. this bit only affects ddc2b mode operation: 0 = ddc2b i2c address is a0/a1 (default) 1 = ddc2b i2c address is ax. least 3 significant address bits are ignored. 3 ddc1_int for ddc1 mode operation only: 0 = no ddc1 interrupt 1 = ddc1 interrupt request. set by hw and should be cleared by sw interrupt service routine. note1: this bit is set in the 9th v clk at ddc1 enable mode. (swenb=1) 2 ddc1en 0 = ddc1 mode is disabled v sync is ignored. the ddc unit will still respond to ddc2b requests. provided i2c enabled.(default) 1 = ddc1 mode is enabled. 1 swhint set by hardware when the ddc unit switches from ddc1 to ddc2b modes. 0 = no interrupt request. 1 = switch to ddc2b mode (interrupt pending) set by hw and should be cleared by sw interrupt service routine. note1: this bit has no connection with swenb. 0mode current mode indication bit: 0 = unit is in ddc1 mode 1 = unit is in ddc2b mode note: when the ddc unit transitions to ddc2b mode, the ddc unit will stay in ddc2b mode until the ddc unit is disabled, or the system is reset.
m psd323x 86/176 table 62. swneb bit function swenb ddc1 or ddc2b mode disabled ddc1 or ddc2b mode enabled ddccon.bit2 = 0 (ddc1 mode disable) or s1con.bit6 = 0 (i 2 c mode disable) ddccon.bit2 = 1 (ddc1 mode enable) or s1con.bit6 = 1 (i 2 c mode enable) 0 in this state, the ddc unit is disabled. the ddc sram cannot be accessed by the mcu. no mcu interrupt and no ddc activity will occur. mcu cannot access internal ddc sram: ddc sram address space is re-assigned to external data space. in this state, the ddc is enabled and the unit is in automatic mode. the ddc sram cannot be accessed by the mcu only the ddc unit has access. mcu cannot access internal ddc sram: data space ff00h-ffffh is dedicated to ddc sram. 1 in this state, the ddc unit is disabled, but with swenb=1, the mcu can access the sram. this state is used to load the ddc sram with the correct data for automatic modes. no mcu interrupt and no ddc activity will occur. mcu can access ddc sram: data space ff00h- ffffh is dedicated to ddc sram. in this state, the ddc sram can be accessed by the mcu. the ddc unit does not use the ddc sram when swenb=1. since the ddc unit is in manual mode, the ddc unit generates an mcu interrupt for each byte transferred. the byte transferred is held in the i 2 c s1dat sfr register. mcu can access ddc sram.
87/176 m psd323x host type detection the detection procedure conforms to the se- quences proposed by vesa monitor display data channel (ddc) specification. the monitor needs to determine the type of host system: n ddc1 or old type host. n ddc2b host (host is master, monitor is always slave) n ddc2b+/ddc2ab(access.bus) host. figure 41. host type detection ai06644 is vsync present? has a command been received? is 2b+/a.b command detected? is ddc2b+/ddc2ab? is it ddc2b command? power on communication isidle edid sent continously using vsync as clock is ddc2 clock present? stop sending of edid switch to ddc2 communication mode ddc2 communication is idle. respond to ddc2b command respond to ddc2b+/ ddc2ab command
m psd323x 88/176 ddc1 protocol ddc1 is primitive and a point to point interface. the monitor is always put at atransmit onlyo mode. in the initialization phase, 9 clock cycles on v clk pin will be given for the internal synchronization. during this period, the sda pin will be kept at high impedance state. if ddc1 hardware mode is used, the following pro- cedure is recommended to proceed ddc1 opera- tion. 1. reset ddc1 enable (by default, ddc1 enable is cleared as low after power-on reset). 2. set swenb as high (the default value is zero.) 3. depending on the data size of edid data, set ex_dat as low (128 bytes) or high (256 bytes). 4. by using bulky moving commands (ddcadr, rambuf involved) to move the entire edid data to ram buffer. 5. reset swenb to low. 6. reset ddcadr to 00h. 7. set ddc1 enable as high. in case swenb is set as high, interrupt service routine is finished within 133 machine cycle in 40mhz system clock. the maximum v sync (v clk ) frequency is 25khz (40 m s). and the 9th clock of v sync (v clk ) is inter- rupt period. so the machine cycle be needed is calculated as below. for example, when 40mhz system clock, 40 m s = 133 x (25ns x 12); 133 machine cycle. 12mhz system clock, 40 m s = 40 x (83.3ns x 12); 40 machine cycle. 8mhz system clock, 40 m s = 26 x (125ns x 12); 26 machine cycle. note: if ex_dat equals to low, it is meant the lower part is occupied by ddc1 operation and the upper part is still free to the system. nevertheless, the effect of the post increment just applies to the part related to ddc1 operation. in other words, the system program is still able to address the loca- tions from 128 to 255 in the ram buffer through movx command but without the facility of the post increment. for example, the case of accessing 200 of the ram buffer: mov r0, #200, and movx a, @r0 figure 42. transmission protocol in the ddc1 interface ai06652 1234567891234567891 b t su(ddc1) t dov hi-z sc vclk ddc1int ddc1en sd t h(vclk) t l(vclk) max=40us bb bbbbb bhiz
89/176 m psd323x ddc2b protocol ddc2b is constructed based on the philips i 2 c in- terface. however, in the level of ddc2b, pc host is fixed as the master and the monitor is always re- garded as the slave. both master and slave can be operated as a transmitter or receiver, but the mas- ter device determines which mode is activated. in this protocol, address pointer is also used. according to ddc2b specification, a0 (for write mode) and a1 (for read mode) are assigned as the default address of monitors. the reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the speci- fied time limit. if software in the slave's side cannot react to the master in time, based on i 2 c protocol, scl pin can be stretched low to inhibit the further action from the master. the transaction can be proceeded in either byte or burst format. figure 43. conceptual structure of the ddc interface ai06645 ddc interrupt vector address ( 0023h ) ddc2b/ddc2ab utilities ddc2b utilities ddc1.ddc2b utilities check mode flag in ddccon mode = 1 mode = 1 mode = 0 i2c serviceroutines i2c interface (h/w) ddc transmitter (h/w) ddc2b/ddc2ab commandreceived ddc2b swenb =1 swenb =0 swenb =1
m psd323x 90/176 usb hardware the characteristics of usb hardware are as fol- lows: n complies with the universal serial bus specification rev. 1.1 n integrated sie (serial interface engine), fifo memory and transceiver n low speed (1.5mbit/s) device capability n supports control endpoint0 and interrupt endpoint1 and 2 n usb clock input must be 6mhz (requires mcu clock frequency to be 12, 24, or 36mhz). the analog front-end is an on-chip generic usb transceiver. it is designed to allow voltage levels equal to v dd from the standard logic to interface with the physical layer of the universal serial bus. it is capable of receiving and transmitting serial data at low speed (1.5mb/s). the sie is the digital-front-end of the usb block. this module recovers the 1.5mhz clock, detects the usb sync word and handles all low-level usb protocols and error checking. the bit-clock recov- ery circuit recovers the clock from the incoming usb data stream and is able to track jitter and fre- quency drift according to the usb specification. the sie also translates the electrical usb signals into bytes or signals. depending upon the device usb address and the usb endpoint. address, the usb data is directed to the correct endpoint on sie interface. the data transfer of this h/w could be of type control or interrupt. the device's usb address and the enabling of the endpoints are programmable in the sie configura- tion header. usb related registers the usb block is controlled via seven registers in the memory: (uadr, ucon0, ucon1, ucon2, uista, uien, and usta). three memory locations on chip which communi- cate the usb block are: n usb endpoint0 data transmit register (udt0) n usb endpoint0 data receive register (udr0) n usb endpoint1 data transmit register (udt1) table 63. usb address register (uadr: 0eeh) table 64. description of the uadr bits 76543210 usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit symbol r/w function 7 usben r/w usb function enable bit. when usben is clear, the usb module will not respond to any tokens from host. reset clears this bit. 6to0 uadd6 to uadd0 r/w specify the usb address of the device. reset clears these bits.
91/176 m psd323x table 65. usb interrupt enable register (uien: 0e9h) table 66. description of the uien bits table 67. usb interrupt status register (uista: 0e8h) 76543210 suspndi rste rstfie txd0ie rxd0ie txd1ie eopie resumi bit symbol r/w function 7 suspndi r/w enable suspnd interrupt 6 rste r/w enable usb reset; also resets the cpu and psd modules when bit is set to '1.' 5 rstfie r/w enable rstf (usb bus reset flag) interrupt 4 txd0ie r/w enable txd0 interrupt 3 rxd0ie r/w enable rxd0 interrupt 2 txd1ie r/w enable txd1 interrupt 1 eopie r/w enable eop interrupt 0 resumi r/w enable usb resume interrupt when it is the suspend mode 76543210 suspnd e rstf txd0f rxd0f txd1f eopf resumf
m psd323x 92/176 table 68. description of the uista bits bit symbol r/w function 7 suspnd r/w usb suspend mode flag. to save power, this bit should be set if a 3ms constant idle state is detected on usb bus. setting this bit stops the clock to the usb and causes the usb module to enter suspend mode. software must clear this bit after the resume flag (resumf) is set while this resume interrupt flag is serviced 6 e e reserved 5rstfr usb reset flag. this bit is set when a valid reset signal state is detected on the d+ and d- lines. when the rste bit in the uien register is set, this reset detection will also generate an internal reset signal to reset the cpu and other peripherals including the usb module. 4 txd0f r/w endpoint0 data transmit flag. this bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag. to enable the next data packet transmission, tx0e must also be set. if txd0f bit is not cleared, a nak handshake will be returned in the next in transactions. reset clears this bit. 3 rxd0f r/w endpoint0 data receive flag. this bit is set after the usb module has received a data packet and responded with ack handshake packet. software must clear this flag after all of the received data has been read. software must also set rx0e bit to one to enable the next data packet reception. if rxd0f bit is not cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. 2 txd1f r/w endpoint1 / endpoint2 data transmit flag. this bit is shared by endpoints 1 and endpoints 2. it is set after the data stored in the shared endpoint 1/ endpoint 2 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag. to enable the next data packet transmission, tx1e must also be set. if txd1f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. 1 eopf r/w end of packet flag. this bit is set when a valid end of packet sequence is detected on the d+ and d-line. software must clear this flag. reset clears this bit. 0 resumf r/w resume flag. this bit is set when usb bus activity is detected while the suspnd bit is set. software must clear this flag. reset clears this bit.
93/176 m psd323x table 69. usb endpoint0 transmit control register (ucon0: 0eah) table 70. description of the ucon0 bits 76543210 tseq0 stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 bit symbol r/w function 7 tseq0 r/w endpoint0 data sequence bit. (0=data0, 1=data1) this bit determines which type of data packet (data0 or data1) will be sent during the next in transaction. toggling of this bit must be controlled by software. reset clears this bit 6 stall0 r/w endpoint0 force stall bit. this bit causes endpoint 0 to return a stall handshake when polled by either an in or out token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 5 tx0e r/w endpoint0 transmit enable. this bit enables a transmit to occur when the usb host controller sends an in token to endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is '0' or the txd0f is set, the usb will respond with a nak handshake to any endpoint 0 in tokens. reset clears this bit. 4 rx0e r/w endpoint0 receive enable. this bit enables a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is '0' or the rxd0f is set, the usb will respond with a nak handshake to any endpoint 0 out tokens. reset clears this bit. 3to0 tp0siz3 to tp0siz0 r/w the number of transmit data bytes. these bits are cleared by reset.
m psd323x 94/176 table 71. usb endpoint1 (and 2) transmit control register (ucon1: 0ebh) table 72. description of the ucon1 bits 76543210 tseq1 ep12sel tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 bit symbol r/w function 7 tseq1 r/w endpoint 1/ endpoint 2 transmit data packet pid. (0=data0, 1=data1) this bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 1 or endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 6 ep12sel r/w endpoint 1/ endpoint 2 transmit selection. (0=endpoint 1, 1=endpoint 2) this bit specifies whether the data inside the registers udt1 are used for endpoint 1 or endpoint 2. if all the conditions for a successful endpoint 2 usb response to a hosts in token are satisfied (txd1f=0, tx1e=1, stall2=0, and ep2e=1) except that the ep12sel bit is configured for endpoint 1, the usb responds with a nak handshake packet. reset clears this bit. 5 tx1e r/w endpoint1 / endpoint2 transmit enable. this bit enables a transmit to occur when the usb host controller send an in token to endpoint 1 or endpoint 2. the appropriate endpoint enable bit, ep1e or ep2e bit in the ucon2 register, should also be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is '0' or txd1f is set, the usb will respond with a nak handshake to any endpoint 1 or endpoint 2 directed in token. reset clears this bit. 4 fresum r/w force resume. this bit forces a resume state (ako on non-idle state) on the usb data lines to initiate a remote wake-up. software should control the timing of the forced resume to be between 10ms and 15ms. setting this bit will not cause the resumf bit to set. 3to0 tp1siz3 to tp1siz0 r/w the number of transmit data bytes. these bits are cleared by reset.
95/176 m psd323x table 73. usb control register (ucon2: 0ech) table 74. description of the ucon2 bits table 75. usb endpoint0 status register (usta: 0edh) table 76. description of the usta bits table 77. usb endpoint0 data receive register (udr0: 0efh) table 78. usb endpoint0 data transmit register (udt0: 0e7h) table 79. usb endpoint1 data transmit register (udt1: 0e6h) 76543210 e e e sout ep2e ep1e stall2 stall1 bit symbol r/w function 7 to 5 e e reserved 4 sout r/w status out is used to automatically respond to the out of a control read transfer 3 ep2e r/w endpoint2 enable. reset clears this bit 2 ep1e r/w endpoint1 enable. reset clears this bit 1 stall2 r/w endpoint2 force stall bit. reset clears this bit 0 stall1 r/w endpoint1 force stall bit. reset clears this bit 76543210 rseq setup in out rp0siz3 rp0siz2 rp0siz1 rp0siz0 bit symbol r/w function 7 rseq r/w endpoint0 receive data packet pid. (0=data0, 1=data1) this bit will be compared with the type of data packet last received for endpoint0 6 setup r setup token detect bit. this bit is set when the received token packet is a sepup token, pid = b1101. 5inr in token detect bit. this bit is set when the received token packet is an in token. 4outr out token detect bit. this bit is set when the received token packet is an out token. 3to0 rp0siz3 to rp0siz0 r the number of data bytes received in a data packet 76543210 udr0.7 udr0.6 udr0.5 udr0.4 udr0.3 udr0.2 udr0.1 udr0.0 76543210 udt0.7 udt0.6 udt0.5 udt0.4 udt0.3 udt0.2 udt0.1 udt0.0 76543210 udt1.7 udt1.6 udt1.5 udt1.4 udt1.3 udt1.2 udt1.1 udt1.0
m psd323x 96/176 the uscl 8-bit prescaler register for usb is at e1h. the uscl should be loaded with a value that results in a clock rate of 6mhz for the usb using the following formula: usb clock input = (f osc / 2) / (prescaler register value +1) where fosc is the mcu clock input frequency. note: usb works only with the mcu clock fre- quencies of 12, 24, or 36mhz. the prescaler val- ues for these frequencies are 0, 1, and 2. table 80. usb sfr memory map sfr addr reg name bit register name reset value comments 7 654321 0 e1 uscl 00 8-bit prescaler for usb logic e6 udt1 udt1.7 udt1.6 udt1.5 udt1.4 udt1.3 udt1.2 udt1.1 udt1.0 00 usb endpt1 data xmit e7 udt0 udt0.7 udt0.6 udt0.5 udt0.4 udt0.3 udt0.2 udt0.1 udt0.0 00 usb endpt0 data xmit e8 uista suspnd e rstf txd0f rxd0f rxd1f eopf resumf 00 usb interrupt status e9 uien suspndie rste rstfie txd0ie rxd0ie txd1ie eopie resumie 00 usb interrupt enable ea ucon0 tseq0 stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 00 usb endpt0 xmit control eb ucon1 tseq1 ep12sel e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 00 usb endpt1 xmit control ec ucon2 e e e sout ep2e ep1e stall2 stall1 00 usb control register ed usta rseq setup in out rp0siz3 rp0siz2 rp0siz1 rp0siz0 00 usb endpt0 status ee uadr usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 00 usb address register ef udr0 udr0.7 udr0.6 udr0.5 udr0.4 udr0.3 udr0.2 udr0.1 udr0.0 00 usb endpt0 data recv
97/176 m psd323x transceiver usb physical layer characteristics. the fol- lowing section describes the m psd323x devices compliance to the chapter 7 electrical section of the usb specification, revision 1.1. the section contains all signaling, and physical layer specifica- tions necessary to describe a low speed usb function. low speed driver characteristics. the m psd323x devices use a differential output driver to drive the low speed usb data signal onto the usb cable. the output swings between the differ- ential high and low state are well balanced to min- imize signal skew. the slew rate control on the driver minimizes the radiated noise and cross talk on the usb cable. the driver's outputs support three-state operation to achieve bi-directional half duplex operation. the m psd323x devices driver tolerates a voltage on the signal pins of -0.5v to 3.6v with respect to local ground reference without damage. the driver tolerates this voltage for 10.0 m s while the driver is active and driving, and tolerates this condition indefinitely when the driver is in its high impedance state. a low speed usb connection is made through an unshielded, untwisted wire cable a maximum of 3 meters in length. the rise and fall time of the sig- nals on this cable are well controlled to reduce rfi emissions while limiting delays, signaling skews and distortions. the m psd323x devices driver reaches the specified static signal levels with smooth rise and fall times, resulting in segments between low speed devices and the ports to which they are connected. figure 44. low speed driver signal waveforms ai06629 signal pins pass output spec levels with minimal reflections and ringing one bit time 1.5 mb/s v ss driver signal pins v se (min) v se (max)
m psd323x 98/176 receiver characteristics the m psd323x devices has a differential input re- ceiver which is able to accept the usb data signal. the receiver features an input sensitivity of at least 200mv when both differential data inputs are in the range of at least 0.8v to 2.5v with respect to its local ground reference. this is the common mode range, as shown in figure 45. the receiver tolerates static input voltages between -0.5v to 3.8v with respect to its local ground reference without damage. in addition to the differential re- ceiver, there is a single-ended receiver for each of the two data lines. the single-ended receivers have a switching threshold between 0.8v and 2.0v (ttl inputs). figure 45. differential input sensitivity over entire common mode range ai06630 0.0 0.0 0.2 0.4 0.6 1.0 0.8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 common mode input voltage (volts) minimum differential sensitivity (volts)
99/176 m psd323x external usb pull-up resistor the usb system specifies a pull-up resistor on the d- pin for low-speed peripherals. the usb spec 1.1 describes a 1.5k w pull-up resistor to a 3.3v supply. an approved alternative method is a 7.5k w pull-up to the usb v cc supply. this alterna- tive is defined for low-speed devices with an inte- grated cable. the chip is specified for the 7.5k w pull-up. this eliminates the need for an external 3.3v regulator, or for a pin dedicated to providing a 3.3v output from the chip. figure 46. usb data signal timing and voltage levels figure 47. receiver jitter tolerance ai06631 vcr d- d+ t r t f 10% 90% 90% 10% v oh v ol ai06632 t jr t jr1 t jr2 consecutive transitions n*t period +t jr1 t period paired transitions n*t period +t jr2 differential data lines
m psd323x 100/176 figure 48. differential to eop transition skew and eop width figure 49. differential data jitter ai06633 receiver eop width t eopr1 ,t eopr2 differential data lines source eop width: t eopt crossover point crossover point extended diff. data to se0 skew n*t period +t deop t period ai06634 consecutive transitions n*t period +t xjr1 t period crossover points paired transitions n*t period +t xjr2 differential data lines
101/176 m psd323x table 81. transceiver dc characteristics note: 1. v dd =5v 10%; v ss =0v; t a =0 to 70 2. level guaranteed for range of v dd = 4.5v to 5.5v 3. with rpu, external idle resistor, 7.5 k 2%, d- to v dd . 4. c l of 50pf(75ns) to 350pf (300ns). 5. measured at crossover point of differential data signals. 6. usb specification indicates 330ns table 82. transceiver ac characteristics note: 1. v dd =5v 10%; v ss =0v; t a =0 to 70 symb parameter test condit ions min max unit v oh static output high 15k w 5% 2.8 3.6 v v ol static output low notes 2,3 e 0.3 v v di differential input sensitivity |(d+) - (d-)|, fig 6.9 0.2 e v v cm differential input common mode fig 6.9 0.8 2.5 v v se single ended receiver threshold e 0.8 2.0 v c in transceiver capacitance e e 20 pf i io data line (d+, d-) leakage 0v<(d+,d-)<3. 3, 10 10 m a r pu external bus pull-up resistance, d- 7.5k w 2% 7.35 7.65 k w r pd external bus pull-down resistance 15k w 5% 14.25 15.75 k w parameter symb min max unit test condition s low speed data rate fdrate 1.4775 1.5225 mbit/s ave. bit rate receiver data jitter tolerance tdjr1 75 75 ns to next transition, differential input sensitivity tdjr2 45 45 ns for paired transition, differential to eop transition skew tdeop 40 100 ns fig 6.10 4 eop width at receiver teopr1 165 e ns rejects as eop 4, 5 eop width at receiver teopr2 675 e ns accepts as eop 4 source eop width teopt 1.25 1.50 m se differential driver jitter tudj1 95 95 ns to next transition, differential driver jitter tudj2 150 150 ns to paired transition, usb data transition rise time tr 75 300 ns notes 1, 2, 3 usb data transition fall time tf 75 300 ns notes 1, 2, 3 rise/fall time matching trfm 80 120 % t r /t f output signal crossover volt age vcrs 1.3 2.0 v e
m psd323x 102/176 psd module n the psd module provides configurable program and data memories to the 8032 cpu core (mcu). in addition, it has its own set of i/o ports and a pld with 16 macrocells for general logic implementation. n ports a,b,c, and d are general purpose programmable i/o ports that have a port architecture which is different from the i/o ports in the mcu module. n the psd module communicates with the mcu module through the internal address, data bus (ao-a15, do-d7) and control signals (rd, wr, psen, ale, reset). the user defines the decoding pld in the psdsoft development tool and can map the resources in the psd module to any program or data address space. figure 50 shows the functional blocks in the psd module. functional overview n 1 or 2 mbit flash memory. this is the main flash memory. it is divided into eight equal- sized blocks that can be accessed with user- specified addresses. n secondary 256 kbit flash boot memory. it is divided into four equal-sized blocks that can be accessed with user-specified addresses. this secondary memory brings the ability to execute code and update the main flash concurrently. n 64 kbit sram. the sram's contents can be protected from a power failure by connecting an external battery. n cpld with 1g output micro cells (omcs} and 24 input micro cells (imcs). the cpld may be used to efficiently implement a variety of logic functions for internal and external control. examples include state machines, loadable shift registers, and loadable counters. n decode pld (dpld) that decodes address for selection of memory blocks in the psd module. n configurable i/o ports (port a,b,c and d) that can be used for the following functions: mcu i/os pld i/os latched mcu address output special function i/os. i/o ports may be configured as open-drain outputs. n built-in jtag compliant serial port allows full- chip in-system programmability (isp). with it, you can program a blank device or reprogram a device in the factory or the field. n internal page register that can be used to expand the 8032 mcu module address space by a factor of 256. n internal programmable power management unit (pmu) that supports a low-power mode called power-down mode. the pmu can automatically detect a lack of the 8032 cpu core activity and put the psd module into power-down mode. n erase/write cycles: flash memory - 100,000 minimum pld - 1,000 minimum data retention: 15 year minimum (for main flash memory, boot, pld and configuration bits)
103/176 m psd323x figure 50. psd module block diagram bus interface wr_, rd_, psen_, ale, reset_, a0-a15 d0 d7 clkin (pd1) clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 1 or 2 mbit primary flash memory 8 sectors vstdby pa0 pa7 pb0 pb7 prog. port port c prog. port port d pc0 pc7 pd1 pd2 address/data/control bus port a ,b & c 2 ext cs to port d 24 input macrocells port a ,b & c 73 73 256 kbit secondary non-volatile memory (boot or data) 4 sectors 64 kbit battery backup sram runtime control and i/o registers sram select perip i/o mode selects macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pc2 ) page register embedded algorithm sector selects sector selects global config. & security ai05797 8 bus interface 8032 bus
m psd323x 104/176 in-system programming (isp) using the jtag signals on port c, the entire psd module device can be programmed or erased without the use of the mcu. the primary flash memory can also be programmed in-system by the mcu executing the programming algorithms out of the secondary memory, or sram. the sec- ondary memory can be programmed the same way by executing out of the primary flash memo- ry. the pld or other psd module configuration blocks can be programmed through the jtag port or a device programmer. table 83 indicates which programming methods can program different func- tional blocks of the psd module. table 83. methods of programming different functional blocks of the psd module functional block jtag programming device programmer iap primary flash memory yes yes yes secondary flash memory yes yes yes pld array (dpld and cpld) yes yes no psd module configuration yes yes no
105/176 m psd323x development system the m psd3200 is supported by psdsoft, a win- dows-based software development tool (win- dows-95, windows-98, windows-nt). a psd module design is quickly and easily produced in a point and click environment. the designer does not need to enter hardware description language (hdl) equations, unless desired, to define psd module pin functions and memory map informa- tion. the general design flow is shown in figure 51. psdsoft is available from our web site (the ad- dress is given on the back page of this data sheet) or other distribution channels. psdsoft directly supports a low cost device pro- grammer from st: flashlink (jtag). the pro- grammer may be purchased through your local distributor/representative, or directly from our web site using a credit card. the m psd3200 is also supported by third party device programmers. see our web site for the current list. figure 51. psdsoft express development tool merge mcu firmware with psd module configuration psd programmer *.obj file flashlink (jtag) a composite object file is created containing mcu firmware and psd configuration c code generation generate c code specific to psd functions user's choice of 8032 compiler/linker *.obj file available for 3rd party programmers (conventional or jtag-isc) mcu firmware hex or s-record format ai05798 define general purpose logic in cpld point and click definition of combin- atorial and registered logic in cpld. access hdl is available if needed define m psd pin and node functions point and click definition of psd pin functions, internal nodes, and mcu system memory map choose m psd
m psd323x 106/176 psd module register description and address offset table 84 shows the offset addresses to the psd module registers relative to the csiop base ad- dress. the csiop space is the 256 bytes of ad- dress that is allocated by the user to the internal psd module registers. table 84 provides brief descriptions of the registers in csiop space. the following section gives a more detailed descrip- tion. table 84. register address offset note: 1. other registers that are not part of the i/o ports. register name port a port b port c port d other 1 description data in 00 01 10 11 reads port pin as input, mcu i/o input mode control 02 03 selects mode between mcu i/o or address out dataout 04051213 stores data for output to port pins, mcu i/o output mode direction 06 07 14 15 configures port pin as input or output drive select 08 09 16 17 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0a 0b 18 reads input macrocells enable out 0c 0d 1a 1b reads the status of the output enable to the i/o port driver output macrocells ab 20 20 read reads output of macrocells ab write loads macrocell flip-flops output macrocells bc 21 21 read reads output of macrocells bc write loads macrocell flip-flops mask macrocells ab 22 22 blocks writing to the output macrocells ab mask macrocells bc 23 23 blocks writing to the output macrocells bc primary flash protection c0 read-only primary flash sector protection secondary flash memory protection c2 read-only psd module security and secondary flash memory sector protection pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd module memory areas in program and/or data space on an individual basis.
107/176 m psd323x psd module detailed operation as shown in figure 15, the psd module con- sists of five major types of functional blocks: n memory block n pld blocks n i/o ports n power management unit (pmu) n jtag interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the psd module has the following memory blocks: primary flash memory secondary flash memory sram the memory select signals for these blocks origi- nate from the decode pld (dpld) and are user- defined in psdsoft express. primary flash memory and secondary flash memory description the primary flash memory is divided evenly into eight equal sectors. the secondary flash memory is divided into four equal sectors. each sector of either memory block can be separately protected from program and erase cycles. flash memory may be erased on a sector-by-sec- tor basis. flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. during a program or erase cycle in flash memory, the status can be output on ready/busy (pc3). this pin is set up using psdsoft express configu- ration. memory block select signals the dpld generates the select signals for all the internal memory blocks (see the section entitled aplds,o page 120). each of the eight sectors of the primary flash memory has a select signal (fs0- fs7) which can contain up to three product terms. each of the four sectors of the secondary flash memory has a select signal (csboot0- csboot3) which can contain up to three product terms. having three product terms for each select signal allows a given sector to be mapped in pro- gram or data space. ready/busy (pc3). this signal can be used to output the ready/busy status of the flash memo- ry. the output on ready/busy (pc3) is a '0' (busy) when flash memory is being written to, or when flash memory is being erased. the output is a 1 (ready) when no write or erase cycle is in progress. memory operation. the primary flash memory and secondary flash memory are addressed through the mcu bus. the mcu can access these memories in one of two ways: n the mcu can execute a typical bus write or read operation . n the mcu can execute a specific flash memory instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash memory to invoke an embedded algorithm. these instructions are summarized in table 85. typically, the mcu can read flash memory using read operations, just as it would read a rom de- vice. however, flash memory can only be altered using specific erase and program instructions. for example, the mcu cannot write a single byte di- rectly to flash memory as it would write a byte to ram. to program a byte into flash memory, the mcu must execute a program instruction, then test the status of the program cycle. this status test is achieved by a read operation or polling ready/busy (pc3). flash memory can also be read by using special instructions to retrieve particular flash device in- formation (sector protect status and id).
m psd323x 108/176 instructions an instruction consists of a sequence of specific operations. each received byte is sequentially de- coded by the psd module and not executed as a standard write operation. the instruction is ex- ecuted when the correct number of bytes are prop- erly received and the time between two consecutive bytes is shorter than the time-out pe- riod. some instructions are structured to include read operations after the initial write opera- tions. the instruction must be followed exactly. any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory resets the device logic into read mode (flash memory is read like a rom device). the flash memory supports the instructions sum- marized in table 85: flash memory: n erase memory by chip or sector n suspend or resume sector erase n program a byte n reset to read mode n read primary flash identifier value n read sector protection status n bypass these instructions are detailed in table 85. for ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cy- cle. address signals a15-a12 are don't care dur- ing the instruction write cycles. however, the appropriate sector select (fs0-fs7 or csboot0-csboot3) must be selected. the primary and secondary flash memories have the same instruction set (except for read primary flash identifier). the sector select signals deter- mine which flash memory is to receive and exe- cute the instruction. the primary flash memory is selected if any one of sector select (fs0-fs7) is high, and the secondary flash memory is selected if any one of sector select (csboot0- csboot3) is high.
109/176 m psd323x table 85. instructions note: 1. all bus cycles are write bus cycles, except the ones with the areado label 2. all values are in hexadecimal: x = don't care. addresses of the form xxxxh, in this table, must be even addresses ra = address of the memory location to be read rd = data read from location ra during the read cycle pa = address of the memory location to be programmed. addresses are latched on the falling edge of write strobe (wr, cntl0). pa is an even address for psd in word programming mode. pd = data word to be programmed at location pa. data is latched on the rising edge of write strobe (wr, cntl0) sa = address of the sector to be erased or verified. the sector select (fs0-fs 7 or csboot0-csbo ot3) of the sector to be erased, or verified, must be active (high). 3. sector select (fs0-fs7 or csboot0-csboot3) signals are active high, and are defined in psdsoft express. 4. only address bits a11-a0 are used in instruction decoding. 5. no unlock or instruction cycles are required when the device is in the read mode 6. the reset instruction is required to return to the read mode after reading the flash id, or after reading the sector protection status, or if the error flag bit (dq5/dq13) goes high. 7. additional sectors to be erased must be written at the end of the sector erase instruction within 80 m s. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. the unlock bypass instruction is required prior to the unlock bypass program instruction. 10. the unlock bypass reset flash instruction is required to return to reading memory data when the device is in the unlock bypass mode. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protection status when in the suspend sector erase mode. the suspend sector erase instruction is valid only during a sector erase cycle. 12. the resume sector erase instruction is valid only during the suspend sector erase mode. 13. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction is intended. the mcu must retrieve, for example, the code from the secondary flash memory when reading the sector protection status of the primary flash memory. instruction fs0-fs7 or csboot0- csboot3 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read 5 1 areado rd @ ra read main flash id 6 1 aah@ x555h 55h@ xaaah 90h@ x555h read id @ xx01h read sector protection 6,8,13 1 aah@ x555h 55h@ xaaah 90h@ x555h read status @ xx02h program a flash byte 13 1 aah@ x555h 55h@ xaaah a0h@ x555h pd@ pa flash sector erase 7,13 1 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 30h@ sa 30h 7 @ next sa flash bulk erase 13 1 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 10h@ x555h suspend sector erase 11 1 b0h@ xxxxh resume sector erase 12 1 30h@ xxxxh reset 6 1 f0h@ xxxxh unlock bypass 1 aah@ x555h 55h@ xaaah 20h@ x555h unlock bypass program 9 1 a0h@ xxxxh pd@ pa unlock bypass reset 10 1 90h@ xxxxh 00h@ xxxxh
m psd323x 110/176 power-down instruction and power-up mode power-up mode. the psd module internal logic is reset upon power-up to the read mode. sector select (fs0-fs7 and csboot0- csboot3) must be held low, and write strobe (wr, cntl0) high, during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of write strobe (wr, cntl0). any write cycle initiation is locked when v cc is below v lko . read under typical conditions, the mcu may read the primary flash memory or the secondary flash memory using read operations just as it would a rom or ram device. alternately, the mcu may use read operations to obtain status information about a program or erase cycle that is currently in progress. lastly, the mcu may use instructions to read special data from these memory blocks. the following sections describe these read functions. read memory contents. primary flash memo- ry and secondary flash memory are placed in the read mode after power-up, chip reset, or a reset flash instruction (see table 85, page 109). the mcu can read the memory contents of the pri- mary flash memory or the secondary flash mem- ory by using read operations any time the read operation is not part of an instruction. read primary flash identifier. the primary flash memory identifier (e7h) is read with an in- struction composed of 4 operations: 3 specific write operations and a read operation (see ta- ble 85). during the read operation, address bits a6, a1, and a0 must be '0,' '0,' and '1,' respective- ly, and the appropriate sector select (fs0-fs7) must be high. read memory sector protection status. the primary flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read opera- tion (see table 85). during the read operation, address bits a6, a1, and a0 must be '0,' '1,' and '0,' respectively, while sector select (fs0-fs7 or csboot0-csboot3) designates the flash memory sector whose protection has to be veri- fied. the read operation produces 01h if the flash memory sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (primary flash memory or secondary flash mem- ory) can also be read by the mcu accessing the flash protection registers in psd i/o space. see the section entitled aflash memory sector pro- tect,o page 115, for register definitions. reading the erase/program status bits. the flash memory provides several status bits to be used by the mcu to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the mcu spends performing these tasks and are defined in table 86, page 111. the status bits can be read as many times as needed. for flash memory, the mcu can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see the section entitled aprogramming flash memory,o page 112, for de- tails. data polling flag (dq7). when erasing or pro- gramming in flash memory, the data polling flag bit (dq7) outputs the complement of the bit being entered for programming/writing on the dq7 bit. once the program instruction or the write oper- ation is completed, the true logic value is read on the data polling flag bit (dq7) (in a read opera- tion). n data polling is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). it must be performed at the address being programmed or at an address within the flash memory sector being erased. n during an erase cycle, the data polling flag bit (dq7) outputs a '0.' after completion of the cycle, the data polling flag bit (dq7) outputs the last bit programmed (it is a '1' after erasing). n if the byte to be programmed is in a protected flash memory sector, the instruction is ignored. n if all the flash memory sectors to be erased are protected, the data polling flag bit (dq7) is reset to '0' for about 100 m s, and then returns to the previous addressed byte. no erasure is performed.
111/176 m psd323x toggle flag (dq6). the flash memory offers an- other way for determining when the program cycle is completed. during the internal write operation and when either the fs0-fs7 or csboot0- csboot3 is true, the toggle flag bit (dq6) tog- gles from '0' to '1' and '1' to '0' on subsequent at- tempts to read any byte of the memory. when the internal cycle is complete, the toggling stops and the data read on the data bus d0-d7 is the addressed memory byte. the device is now accessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. n the toggle flag bit (dq6) is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). n if the byte to be programmed belongs to a protected flash memory sector, the instruction is ignored. n if all the flash memory sectors selected for erasure are protected, the toggle flag bit (dq6) toggles to '0' for about 100 m s and then returns to the previous addressed byte. error flag (dq5). during a normal program or erase cycle, the error flag bit (dq5) is to '0.' this bit is set to '1' when there is a failure during flash memory byte program, sector erase, or bulk erase cycle. in the case of flash memory programming, the er- ror flag bit (dq5) indicates the attempt to program a flash memory bit from the programmed state, '0', to the erased state, '1,' which is not valid. the error flag bit (dq5) may also indicate a time-out condition while attempting to program a byte. in case of an error in a flash memory sector erase or byte program cycle, the flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. other flash memory sectors may still be used. the error flag bit (dq5) is reset after a reset flash instruction. erase time-out flag (dq3). the erase time- out flag bit (dq3) reflects the time-out period al- lowed between two consecutive sector erase in- structions. the erase time-out flag bit (dq3) is reset to '0' after a sector erase cycle for a time pe- riod of 100 m s + 20% unless an additional sector erase instruction is decoded. after this time peri- od, or when the additional sector erase instruction is decoded, the erase time-out flag bit (dq3) is set to '1.' table 86. status bit note: 1. x = not guaranteed value, can be read either '1' or '0.' 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fs0-fs7 and csboot0-csboot 3 are active high. functional block fs0-fs7/csboot0- csboot3 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash memory v ih data polling toggle flag error flag x erase time- out xxx
m psd323x 112/176 programming flash memory flash memory must be erased prior to being pro- grammed. a byte of flash memory is erased to all '1s' (ffh), and is programmed by setting selected bits to '0.' the mcu may erase flash memory all at once or by-sector, but not byte-by-byte. howev- er, the mcu may program flash memory byte-by- byte. the primary and secondary flash memories re- quire the mcu to send an instruction to program a byte or to erase sectors (see table 85). once the mcu issues a flash memory program or erase instruction, it must check for the status bits for completion. the embedded algorithms that are invoked support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or ready/busy (pc3). data polling. polling on the data polling flag bit (dq7) is a method of checking whether a program or erase cycle is in progress or has completed. figure 52 shows the data polling algorithm. when the mcu issues a program instruction, the embedded algorithm begins. the mcu then reads the location of the byte to be programmed in flash memory to check status. the data polling flag bit (dq7) of this location becomes the complement of b7 of the original data byte to be programmed. the mcu continues to poll this location, comparing the data polling flag bit (dq7) and monitoring the er- ror flag bit (dq5). when the data polling flag bit (dq7) matches b7 of the original data, and the er- ror flag bit (dq5) remains '0,' the embedded algo- rithm is complete. if the error flag bit (dq5) is '1,' the mcu should test the data polling flag bit (dq7) again since the data polling flag bit (dq7) may have changed simultaneously with the error flag bit (dq5) (see figure 52). the error flag bit (dq5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the mcu at- tempted to program a '1' to a bit that was not erased (not erased is logic '0'). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the flash memory with the byte that was intended to be written. when using the data polling method during an erase cycle, figure 52 still applies. however, the data polling flag bit (dq7) is '0' until the erase cy- cle is complete. a '1' on the error flag bit (dq5) in- dicates a time-out condition on the erase cycle; a '0' indicates no error. the mcu can read any loca- tion within the sector being erased to get the data polling flag bit (dq7) and the error flag bit (dq5). psdsoft express generates ansi c code func- tions which implement these data polling algo- rithms. figure 52. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 =1 dq7 = data yes no
113/176 m psd323x data toggle. checking the toggle flag bit (dq6) is a method of determining whether a pro- gram or erase cycle is in progress or has complet- ed. figure 53 shows the data toggle algorithm. when the mcu issues a program instruction, the embedded algorithm begins. the mcu then reads the location of the byte to be programmed in flash memory to check status. the toggle flag bit (dq6) of this location toggles each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this loca- tion, checking the toggle flag bit (dq6) and mon- itoring the error flag bit (dq5). when the toggle flag bit (dq6) stops toggling (two consecutive reads yield the same value), and the error flag bit (dq5) remains '0,' the embedded algorithm is complete. if the error flag bit (dq5) is '1,' the mcu should test the toggle flag bit (dq6) again, since the toggle flag bit (dq6) may have changed simultaneously with the error flag bit (dq5) (see figure 53). the error flag bit(dq5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the mcu at- tempted to program a '1' to a bit that was not erased (not erased is logic '0'). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to flash memory with the byte that was intended to be written. when using the data toggle method after an erase cycle, figure 53 still applies. the toggle flag bit (dq6) toggles until the erase cycle is complete. a 1 on the error flag bit (dq5) indicates a time-out condition on the erase cycle; a '0' indi- cates no error. the mcu can read any location within the sector being erased to get the toggle flag bit (dq6) and the error flag bit (dq5). psdsoft express generates ansi c code func- tions which implement these data toggling algo- rithms. figure 53. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 =1 no yes dq6 = toggle
m psd323x 114/176 unlock bypass. the unlock bypass instructions allow the system to program bytes to the flash memories faster than using the standard program instruction. the unlock bypass mode is entered by first initiating two unlock cycles. this is followed by a third write cycle containing the unlock by- pass code, 20h (as shown in table 85). the flash memory then enters the unlock bypass mode. a two-cycle unlock bypass program in- struction is all that is required to program in this mode. the first cycle in this instruction contains the unlock bypass program code, a0h. the sec- ond cycle contains the program address and data. additional data is programmed in the same man- ner. these instructions dispense with the initial two unlock cycles required in the standard pro- gram instruction, resulting in faster total flash memory programming. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset flash instructions are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset flash in- struction. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don't care for both cycles. the flash memory then returns to read mode. erasing flash memory flash bulk erase. the flash bulk erase instruc- tion uses six write operations followed by a read operation of the status register, as de- scribed in table 85. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading the error flag bit (dq5), the toggle flag bit (dq6), and the data polling flag bit (dq7), as detailed in the section entitled apro- gramming flash memory,o page 112. the error flag bit (dq5) returns a '1' if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the memory with 00h because the psd module automatically does this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory does not accept any instructions. flash sector erase. the sector erase instruc- tion uses six write operations, as described in table 85. additional flash sector erase codes and flash memory sector addresses can be writ- ten subsequently to erase other flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100 m s. the input of a new sector erase code restarts the time- out period. the status of the internal timer can be monitored through the level of the erase time-out flag bit (dq3). if the erase time-out flag bit (dq3) is '0,' the sector erase instruction has been received and the time-out period is counting. if the erase time-out flag bit (dq3) is '1,' the time-out period has expired and the embedded algorithm is busy erasing the flash memory sector(s). before and during erase time-out, any instruction other than suspend sector erase and resume sector erase instructions abort the cycle that is currently in progress, and reset the device to read mode. during a sector erase, the memory status may be checked by reading the error flag bit (dq5), the toggle flag bit (dq6), and the data polling flag bit (dq7), as detailed in the section entitled apro- gramming flash memory,o page 112. during execution of the erase cycle, the flash memory accepts only reset and suspend sec- tor erase instructions. erasure of one flash mem- ory sector may be suspended, in order to read data from another flash memory sector, and then resumed. suspend sector erase. when a sector erase cycle is in progress, the suspend sector erase in- struction can be used to suspend the cycle by writ- ing 0b0h to any address when an appropriate sector select (fs0-fs7 or csboot0-csboot3) is high. (see table 85). this allows reading of data from another flash memory sector after the erase cycle has been suspended. suspend sec- tor erase is accepted only during an erase cycle and defaults to read mode. a suspend sector erase instruction executed during an erase time- out period, in addition to suspending the erase cy- cle, terminates the time out period. the toggle flag bit (dq6) stops toggling when the internal logic is suspended. the status of this bit must be monitored at an address within the flash memory sector being erased. the toggle flag bit (dq6) stops toggling between 0.1 m sand15 m saf- ter the suspend sector erase instruction has been executed. the flash memory is then automatically set to read mode. if an suspend sector erase instruction was exe- cuted, the following rules apply: attempting to read from a flash memory sector that was being erased outputs invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and only responds to resume sector erase and reset flash instructions (read is an operation and is allowed).
115/176 m psd323x if a reset flash instruction is received, data in the flash memory sector that was being erased is invalid. resume sector erase. if a suspend sector erase instruction was previously executed, the erase cycle may be resumed with this instruction. the resume sector erase instruction consists of writing 030h to any address while an appropriate sector select (fs0-fs7 or csboot0-csboot3) is high. (see table 85.) specific features flash memory sector protect. each primary and secondary flash memory sector can be sepa- rately protected against program and erase cy- cles. sector protection provides additional data security because it disables all program or erase cycles. this mode can be activated through the jtag port or a device programmer. sector protection can be selected for each sector using the psdsoft express configuration pro- gram. this automatically protects selected sectors when the device is programmed through the jtag port or a device programmer. flash memory sec- tors can be unprotected to allow updating of their contents using the jtag port or a device pro- grammer. the mcu can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash memory sector is ignored by the device. the verify operation results in a read of the protected data. this allows a guarantee of the retention of the pro- tection status. the sector protection status can be read by the mcu through the flash memory protection regis- ters (in the csiop block). see table 87 and table 88. table 87. sector protection/security bit definition flash protection register note: 1. bit definitions: sec_prot 1 = primary flash memory or secondary flash memory sector is write-protected. sec_prot 0 = primary flash memory or secondary flash memory sector is not write-protected. table 88. sector protection/security bit definition secondary flash protection register note: 1. bit definitions: sec_prot 1 = secondary flash memory sector is write-protected. sec_prot 0 = secondary flash memory sector is not write-protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot
m psd323x 116/176 reset flash. the reset flash instruction con- sists of one write cycle (see table 85). it can also be optionally preceded by the standard two write decoding cycles (writing aah to 555h and 55h to aaah). it must be executed after: reading the flash protection status or flash id an error condition has occurred (and the device has set the error flag bit (dq5) to '1' during a flash memory program or erase cycle. the reset flash instruction puts the flash memo- ry back into normal read mode. if an error condi- tion has occurred (and the device has set the error flag bit (dq5) to '1' the flash memory is put back into normal read mode within 25 m s of the reset flash instruction having been issued. the reset flash instruction is ignored when it is issued dur- ing a program or bulk erase cycle of the flash memory. the reset flash instruction aborts any on-going sector erase cycle, and returns the flash memory to the normal read mode within 25 m s. reset (reset) signal. a pulse on reset (re- set) aborts any cycle that is in progress, and re- sets the flash memory to the read mode. when the reset occurs during a program or erase cycle, the flash memory takes up to 25 m s to return to the read mode. it is recommended that the reset (reset) pulse (except for power-on reset, as described on page 140) be at least 25 m s so that the flash memory is always ready for the mcu to retreive the bootstrap instructions after the reset cycle is complete. sram the sram is enabled when sram select (rs0) from the dpld is high. sram select (rs0) can contain up to two product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to voltage stand-by (v stby , pc2). if you have an external battery connected to the m psd3200, the contents of the sram are retained in the event of a power loss. the contents of the sram are re- tained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the bat- tery voltage, an internal power switch-over to the battery occurs. pc4 can be configured as an output that indicates when power is being drawn from the external bat- tery. battery-on indicator (v baton , pc4) is high with the supply voltage falls below the battery volt- age and the battery on voltage stand-by (v stby , pc2) is supplying power to the internal sram. sram select (rs0), voltage stand-by (v stby , pc2) and battery-on indicator (v baton , pc4) are all configured using psdsoft express configura- tion. sector select and sram select sector select (fs0-fs7, csboot0-csboot3) and sram select (rs0) are all outputs of the dpld. they are setup by writing equations for them in psdsoft express. the following rules ap- ply to the equations for these signals: 1. primary flash memory and secondary flash memory sector select signals must not be larg- er than the physical sector size. 2. any primary flash memory sector must not be mapped in the same memory space as another flash memory sector. 3. a secondary flash memory sector must not be mapped in the same memory space as another secondary flash memory sector. 4. sram, i/o, and peripheral i/o spaces must not overlap. 5. a secondary flash memory sector may overlap a primary flash memory sector. in case of over- lap, priority is given to the secondary flash memory sector. 6. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority is giv- en to the sram, i/o, or peripheral i/o.
117/176 m psd323x example. fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 always accesses the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) automatically addresses secondary flash memory segment 0. any address greater than 9fffh accesses the primary flash memory seg- ment 0. you can see that half of the primary flash memory segment 0 and one-fourth of secondary flash memory segment 0 cannot be accessed in this example. note: an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 54 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest. memory select configuration in program and data spaces. the mcu core has separate ad- dress spaces for program memory and data memory. any of the memories within the psd module can reside in either space or both spac- es. this is controlled through manipulation of the vm register that resides in the csiop space. the vm register is set using psdsoft express to have an initial value. it can subsequently be changed by the mcu so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and pri- mary flash memory in the data space at boot-up, and secondary flash memory in the program space at boot-up, and later swap the primary and secondary flash memories. this is easily done with the vm register by using psdsoft express configuration to configure it for boot-up and hav- ing the mcu change it when desired. table 89 de- scribes the vm register. figure 54. priority level of memory and i/o components in the psd module table 89. vm register level 1 sram, i/o, or peripheral i/o level 2 secondar y non-volatile memory highest priority level 3 primary flash memory bit 7 pio_en bit 6 bit 5 bit 4 primary fl_data bit 3 secondary data bit 2 primary fl_code bit 1 secondary code bit 0 sram_code 0 = disable pio mode not used not used 0=rd can't access flash memory 0 = rd can't access secondary flash memory 0 = psen can't access flash memory 0 = psen can't access secondary flash memory 0 = psen can't access sram 1= enable pio mode not used not used 1=rd access flash memory 1 = rd access secondary flash memory 1 = psen access flash memory 1 = psen access secondary flash memory 1 = psen access sram
m psd323x 118/176 separate space mode. program space is sepa- rated from data space. for example, program se- lect enable (psen) is used to access the program code from the primary flash memory, while read strobe (rd) is used to access data from the sec- ondary flash memory, sram and i/o port blocks. this configuration requires the vm register to be set to 0ch (see figure 55). combined space modes. the program and data spaces are combined into one memory space that allows the primary flash memory, sec- ondary flash memory, and sram to be accessed by either program select enable (psen) or read strobe (rd). for example, to configure the prima- ry flash memory in combined space, bits b2 and b4 of the vm register are set to '1' (see figure 56). figure 55. separate space mode figure 56. combined space mode primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 cs cs cs oe oe rd psen oe ai02869c primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai02870c
119/176 m psd323x page register the 8-bit page register increases the addressing capability of the mcu core by a factor of up to 256. the contents of the register can also be read by the mcu. the outputs of the page register (pgr0-pgr7) are inputs to the dpld decoder and can be included in the sector select (fs0- fs7, csboot0-csboot3), and sram select (rs0) equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. figure 57 shows the page register. the eight flip- flops in the register are connected to the internal data bus d0-d7. the mcu can write to or read from the page register. the page register can be accessed at address location csiop + e0h. figure 57. page register reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal psd module selects and logic pld pgr4 pgr5 pgr6 pgr7 ai05799
m psd323x 120/176 plds the plds bring programmable logic functionality to the m psd. after specifying the logic for the plds in psdsoft express, the logic is pro- grammed into the device and available upon pow- er-up. table 90. dpld and cpld inputs note: 1. these inputs are not available in the 52-pin package. the psd module contains two plds: the de- code pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in the section enti- tled adecode pld (dpld),o page 122, and the section entitled acomplex pld (cpld),o page 123. figure 58 shows the configuration of the plds. the dpld performs address decoding for select signals for psd module components, such as memory, registers, and i/o ports. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the out- put macrocells (omc), input macrocells (imc), and the and array. the cpld can also be used to generate external chip select (ecs1-ecs2) signals. the and array is used to form product terms. these product terms are specified using psdsoft. the pld input signals consist of internal mcu sig- nals and external inputs from the i/o ports. the in- put signals are shown in table 90. the turbo bit in psd module the plds can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. resetting the turbo bit to '0' (bit 3 of pmmr0) automatically places the plds into standby if no inputs are changing. turning the turbo mode off increases propagation delays while reducing power con- sumption. see the section entitled apower man- agement,o page 136, on how to set the turbo bit. additionally, five bits are available in pmmr2 to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. input source input name number of signals mcu address bus a15-a0 16 mcu control signals psen, rd, wr, ale 4 reset rst 1 power-down pdn 1 port a input macrocells 1 pa7-pa0 8 port b input macrocells pb7-pb0 8 port c input macrocells pc7-pc0 8 port d inputs pd2-pd1 2 page register pgr7-pgr0 8 macrocell ab feedback mcellab.fb7- fb0 8 macrocell bc feedback mcellbc.fb7- fb0 8 flash memory program status bit ready/busy 1
121/176 m psd323x figure 58. pld diagram note: 1. ports a is not available in the 52-pin package pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select secondary non-volatile memory selects decode pld page register peripheral selects cpld pt alloc. macrocell alloc. mcellab mcellbc direct macrocell access from mcu data bus 24 input macrocell (port a,b,c) 16 output macrocell i/o ports primary flash memory selects 2 port d inputs to port a or b 1 to port b or c data bus 8 8 8 4 1 1 2 external chip selects to port d 2 16 24 output macrocell feedback ai06600 73 73
m psd323x 122/176 decode pld (dpld) the dpld, shown in figure 59, is used for decod- ing the address for psd module and external components. the dpld can be used to generate the following decode signals: n 8 sector select (fs0-fs7) signals for the primary flash memory (three product terms each) n 4 sector select (csboot0-csboot3) signals for the secondary flash memory (three product terms each) n 1 internal sram select (rs0) signal (two product terms) n 1 internal csiop select signal (selects the psd module registers) n 2 internal peripheral select signals (peripheral i/o mode). figure 59. dpld logic array note: 1. port a inputs are not available in the 52-pin package 2. inputs from the mcu module (inputs) (24) (8) (16) (1) pdn (apd output) i/o ports (port a,b,c) 1 (8) pgr0 -pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] 2 (2) (4) pd [ 2:1 ] psen, rd, wr, ale 2 (1) (1) reset 2 rd_bsy rs0 csiop psel0 psel1 8 primary flash memory sector selects sram select i/o decoder select peripheral i/o mode select csboot 0 csboot 1 csboot 2 csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 2 ai06601 fs1 fs2 fs3 fs6 fs5 fs4 1 1 1
123/176 m psd323x complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate external chip select (ecs1-ecs2), routed to port d. although external chip select (ecs1-ecs2) can be produced by any output macrocell (omc), these external chip select (ecs1-ecs2) on port d do not consume any output macrocells (omc). as shown in figure 58, the cpld has the following blocks: n 24 input macrocells (imc) n 16 output macrocells (omc) n macrocell allocator n product term allocator n and array capable of generating up to 137 product terms n four i/o ports. each of the blocks are described in the sections that follow. the input macrocells (imc) and output macrocells (omc) are connected to the psd module inter- nal data bus and can be directly accessed by the mcu. this enables the mcu software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and array as required in most standard pld macrocell architectures. figure 60. macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable (oe) macrocell feedback i/o port input ale pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select macrocell to i/o port alloc. cpld output to other i/o ports pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai06602
m psd323x 124/176 output macrocell (omc) eight of the output macrocells (omc) are con- nected to ports a and b pins and are named as mcellab0-mcellab7. the other eight macrocells are connected to ports b and c pins and are named as mcellbc0-mcellbc7. if an mcellab out- put is not assigned to a specific pin in psdsoft, the macrocell allocator block assigns it to either port a or b. the same is true for a mcellbc output on port b or c. table 91 shows the macrocells and port assignment. the output macrocell (omc) architecture is shown in figure 61. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other output macrocells (omc). the polarity of the product term is controlled by the xor gate. the output macrocell (omc) can im- plement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the output macrocell (omc) block can be configured as a d, t, jk, or sr type in ps- dsoft. the flip-flop's clock, preset, and clear inputs may be driven from a product term of the and ar- ray. alternatively, clkin (pd1) can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. table 91. output macrocell port and data bit assignments note: 1. mcellab0-mcellab7 can only be assigned to port b in the 52-pin package output macrocell port assignment 1 native product terms maximum borrowed product terms data bit for loadin g or reading mcellab0 port a0, b0 3 6 d0 mcellab1 port a1, b1 3 6 d1 mcellab2 port a2, b2 3 6 d2 mcellab3 port a3, b3 3 6 d3 mcellab4 port a4, b4 3 6 d4 mcellab5 port a5, b5 3 6 d5 mcellab6 port a6, b6 3 6 d6 mcellab7 port a7, b7 3 6 d7 mcellbc0 port b0, c0 4 5 d0 mcellbc1 port b1, c1 4 5 d1 mcellbc2 port b2, c2 4 5 d2 mcellbc3 port b3, c3 4 5 d3 mcellbc4 port b4, c4 4 6 d4 mcellbc5 port b5, c5 4 6 d5 mcellbc6 port b6, c6 4 6 d6 mcellbc7 port b7, c7 4 6 d7
125/176 m psd323x product term allocator the cpld has a product term allocator. psdsoft uses the product term allocator to borrow and place product terms from one macrocell to anoth- er. the following list summarizes how product terms are allocated: n mcellab0-mcellab7 all have three native product terms and may borrow up to six more n mcellbc0-mcellbc3 all have four native product terms and may borrow up to five more n mcellbc4-mcellbc7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. if an equation requires more product terms than are available to it, then aexternalo product terms are required, which consume other output macro- cells (omc). if external product terms are used, extra delay is added for the equation that required the extra product terms. this is called product term expansion. psdsoft express performs this expansion as needed. loading and reading the output macrocells (omc). the output macrocells (omc) block oc- cupies a memory location in the mcu address space, as defined by the csiop block (see the section entitled ai/o ports (psd module),o on page 127). the flip-flops in each of the 16 output macrocells (omc) can be loaded from the data bus by a mcu. loading the output macrocells (omc) with data from the mcu takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as load- able counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the output macrocells (omc) on the trailing edge of write strobe (wr, edge loading) or during the time that write strobe (wr) is active (level loading). the method of loading is specified in psdsoft express config- uration. figure 61. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin macrocell allocator mcu data bus d [ 7:0] direction register clear (.re) programmable ff (d /t/jk /sr) wr enable (.oe) preset(.pr) rd macrocell cs ai06617
m psd323x 126/176 the omc mask register. there is one mask register for each of the two groups of eight output macrocells (omc). the mask registers can be used to block the loading of data to individual out- put macrocells (omc). the default value for the mask registers is 00h, which allows loading of the output macrocells (omc). when a given bit in a mask register is set to a '1,' the mcu is blocked from writing to the associated output macrocells (omc). for example, suppose mcellab0- mcellab3 are being used for a state machine. you would not want a mcu write to mcellab to over- write the state machine registers. therefore, you would want to load the mask register for mcellab (mask macrocell ab) with the value 0fh. the output enable of the omc. the output macrocells (omc) block can be connected to an i/ o port pin as a pld output. the output enable of each port pin driver is controlled by a single prod- uct term from the and array, ored with the direc- tion register output. the pin is enabled upon power-up if no output enable equation is defined and if the pin is declared as a pld output in psd- soft express. if the output macrocell (omc) output is declared as an internal node and not as a port pin output in the psdabel file, the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array. input macrocells (imc) the cpld has 24 input macrocells (imc), one for each pin on ports a, b, and c. the architecture of the input macrocells (imc) is shown in figure 62. the input macrocells (imc) are individually config- urable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the input macrocells (imc) can be read by the mcu through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale). each product term output is used to latch or clock four input macro- cells (imc). port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the input macrocells (imc) are specified by equations written in psdsoft (see ap- plication note an1171 ). outputs of the input mac- rocells (imc) can be read by the mcu via the imc buffer. see the section entitled ai/o ports (psd module),o page 127. figure 62. input macrocell output macrocells bc and macrocell ab pt pt feedback and array pld input bus port driver i/o pin mcu data bus d [ 7:0] direction register mux mux ale pt q q d d g latch input macrocell enable (.oe ) dff input macrocell _rd ai06603
127/176 m psd323x i/o ports (psd module) there are four programmable i/o ports: ports a, b, c, and d in the psd module. each of the ports is eight bits except port d, which is 3 bits. each port pin is individually user configurable, thus al- lowing multiple functions per port. the ports are configured using psdsoft express configuration or by the mcu writing to on-chip registers in the csiop space. port a is not available in the 52-pin package. the topics discussed in this section are: n general port architecture n port operating modes n port configuration registers (pcr) n port data registers n individual port functionality. general port architecture the general architecture of the i/o port block is shown in figure 63. individual port architectures are shown in figure 65 to figure 68. in general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. exceptions are noted. as shown in figure 63, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the control registers (ports a and b only) and psdsoft express configuration. inputs to the multiplexer include the following: n output data from the data out register n latched address outputs n cpld macrocell output n external chip select (ecs1-ecs2) from the cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the mcu. the data out and macrocell outputs, direc- tion and control registers, and port pin input are all connected to the port data buffer (pdb). figure 63. general i/o port architecture mcu data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term (.oe) ext cs ale read mux p d b cpld -input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai06604
m psd323x 128/176 the port pin's tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdsoft, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the mcu. the port data buffer (pdb) feedback path allows the mcu to check the contents of the registers. ports a, b, and c have embedded input macro- cells (imc). the input macrocells (imc) can be configured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by address strobe (ale) or a product term from the pld and array. the outputs from the input macrocells (imc) drive the pld input bus and can be read by the mcu. see the section entitled ain- put macrocell,o page 126. port operating modes the i/o ports have several modes of operation. some modes can be defined using psdsoft, some by the mcu writing to the control registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be pro- grammed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the mcu can be done so dynamically at run-time. the pld i/o, data port, address input, and peripheral i/o modes are the only modes that must be defined before program- ming the device. all other modes can be changed by the mcu at run-time. see application note an1171 for more detail. table 92 summarizes which modes are available on each port. table 95 shows how and where the different modes are configured. each of the port operating modes are described in the following sections. mcu i/o mode in the mcu i/o mode, the mcu uses the i/o ports block to expand its own i/o ports. by setting up the csiop space, the ports on the psd module are mapped into the mcu address space. the ad- dresses of the ports are listed in table 84. a port pin can be put into mcu i/o mode by writing a '0' to the corresponding bit in the control regis- ter. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. see the section entitled aperipheral i/o mode,o page 128. when the pin is configured as an out- put, the content of the data out register drives the pin. when configured as an input, the mcu can read the port input through the data in buffer. see figure 63, page 127. ports c and d do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if equations are written for them in ps- dabel. pld i/o mode the pld i/o mode uses a port as an input to the cpld's input macrocells (imc), and/or as an out- put from the cpld's output macrocells (omc). the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by resetting the corresponding bit in the direction register to '0.' the corresponding bit in the direction register must not be set to '1' if the pin is defined for a pld input signal in psdsoft. the pld i/o mode is specified in psdsoft by declaring the port pins, and then writing an equation assigning the pld i/ o to a port. address out mode address out mode can be used to drive latched mcu addresses on to the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a '1' for pins to use address out mode. this must be done by the mcu at run-time. see table 94 for the address output pin assignments on ports a and b for various mcus. peripheral i/o mode peripheral i/o mode can be used to interface with external peripherals. in this mode, all of port a serves as a tri-state, bi-directional data buffer for the mcu. peripheral i/o mode is enabled by set- ting bit 7 of the vm register to a '1.' figure 64 shows how port a acts as a bi-directional buffer for the mcu data bus if peripheral i/o mode is en- abled. an equation for psel0 and/or psel1 must be written in psdsoft. the buffer is tri-stated when psel0 or psel1 is low (not active). the psen signal should be aandedo in the psel equations to disable the buffer when psel resides in the data space. jtag in-system programming (isp) port c is jtag compliant, and can be used for in- system programming (isp). for more information on the jtag port, see the section entitled apro- gramming in-circuit using the jtag se- rial interface,o page 142.
129/176 m psd323x figure 64. peripheral i/o mode table 92. port operating modes note: 1. jtag pins (tms, tck, tdi, tdo) are dedicated pins. 2. port a is not available in the 52-pin package. table 93. port operating mode settings note: 1. n/a = not applicable 2. the direction of the port a,b,c, and d pins are controlled by the direction register ored with the individual output enable product term (.oe) from the cpld and array. table 94. i/o port latched address output assignments port mode port a 2 port b port c port d mcui/o yesyesyesyes pld i/o mcellab outputs mcellbc outputs additional ext. cs outputs pld inputs ye s no no ye s yes yes no yes no yes no yes no no ye s ye s address out yes (a7 0) yes (a7 0) no no peripheral i/o yes no no no jtag isp no no yes 1 no mode defined in psdsoft control register setting direction register setting vm register setting mcu i/o declare pins only 0 1 = output, 0 = input (note 2 ) n/a pld i/o logic equations n/a (note 2 ) n/a address out (port a,b) declare pins only 1 1 (note 2 ) n/a peripheral i/o (port a) logic equations (psel0 & 1) n/a n/a pio bit = 1 port a (pa3-pa0) port a (pa7-pa4) port b (pb3-pb0) port b (pb7-pb4) address a3-a0 address a7-a4 address a3-a0 address a7-a4 rd psel0 psel1 psel vm register bit 7 wr pa0 - pa7 d0 - d7 data bus ai02886
m psd323x 130/176 port configuration registers (pcr) each port has a set of port configuration regis- ters (pcr) used for configuration. the contents of the registers can be accessed by the mcu through normal read/write bus cycles at the addresses given in table 84. the addresses in table 84 are the offsets in hexadecimal from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three port configuration registers (pcr), shown in table 95, are used for setting the port configurations. the default power-up state for each register in table 95 is 00h. control register. any bit reset to '0' in the con- trol register sets the corresponding port pin to mcu i/o mode, and a '1' sets it to address out mode. the default mode is mcu i/o. only ports a and b have an associated control register. direction register. the direction register, in conjunction with the output enable (except for port d), controls the direction of data flow in the i/o ports. any bit set to '1' in the direction register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. the de- fault mode for all port pins is input. figure 65, page 132 and figure 66, page 133 show the port architecture diagrams for ports a/b and c, respectively. the direction of data flow for ports a, b, and c are controlled not only by the di- rection register, but also by the output enable product term from the pld and array. if the out- put enable product term is not active, the direction register has sole control of a given pin's direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in table 98. since port d only contains two pins (shown in figure 68), the direction register for port d has only two bits active. drive select register. the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a '1.' the default pin drive is cmos. note: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive reg- ister is set to '1.' the default rate is slow slew. table 99, page 131 shows the drive register for ports a, b, c, and d. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. table 95. port configuration registers (pcr) note: 1. see table 99 for drive register bit definition. table 96. port pin direction control, output enable p.t. not defined table 97. port pin direction control, output enable p.t. defined table 98. port direction assignment example register name port mcu access control a,b write/read direction a,b,c,d write/read drive select 1 a,b,c,d write/read direction register bit port pin mode 0 input 1 output direction register bit output enable p.t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000111
131/176 m psd323x port data registers the port data registers, shown in table 100, are used by the mcu to write data to or read data from the ports. table 100 shows the register name, the ports having each register type, and mcu access for each register type. the registers are described below. data in. port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin in- put is read through the data in buffer. data out register. stores output data written by the mcu in the mcu i/o output mode. the con- tents of the register are driven out to the pins if the direction register or the output enable product term is set to '1.' the contents of the register can also be read back by the mcu. output macrocells (omc). the cpld output macrocells (omc) occupy a location in the mcu's address space. the mcu can read the output of the output macrocells (omc). if the omc mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops. see the sec- tion entitled aplds,o page 120. omc mask register. each omc mask register bit corresponds to an output macrocell (omc) flip- flop. when the omc mask register bit is set to a '1,' loading data into the output macrocell (omc) flip-flop is blocked. the default value is '0' or un- blocked. input macrocells (imc). the input macrocells (imc) can be used to latch or store external inputs. the outputs of the input macrocells (imc) are rout- ed to the pld input bus, and can be read by the mcu. see the section entitled aplds,o page 120. enable out. the enable out register can be read by the mcu. it contains the output enable values for a given port. a '1' indicates the driver is in out- put mode. a '0' indicates the driver is in tri-state and the pin is in input mode. table 99. drive register pin assignment note: 1. na = not applicable. table 100. port data registers drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain slew rate slew rate slew rate slew rate port b open drain open drain open drain open drain slew rate slew rate slew rate slew rate port c open drain open drain open drain open drain open drain open drain open drain open drain port d na 1 na 1 na 1 na 1 na 1 slew rate slew rate na 1 register name port mcu access data in a,b,c,d read input on pin data out a,b,c,d write/read output macrocell a,b,c read outputs of macrocells write loading macrocells flip-flop mask macrocell a,b,c write/read prevents loading into a given macrocell input macrocell a,b,c read outputs of the input macrocells enable out a,b,c read the output enable control of the port driver
m psd323x 132/176 ports a and b functionality and structure ports a and b have similar functionality and struc- ture, as shown in figure 65. the two ports can be configured to perform one or more of the following functions: n mcu i/o mode n cpld output macrocells mcellab7-mcellab0 can be connected to port a or port b. mcellbc7- mcellbc0 can be connected to port b or port c. n cpld input via the input macrocells (imc). n latched address output provide latched address output as per table 94. n open drain/slew rate pins pa3-pa0 and pb3-pb0 can be configured to fast slew rate, pins pa7-pa4 and pb7-pb4 can be configured to open drain mode. n peripheral mode port a only (80-pin package) figure 65. port a and port b structure mcu data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term (.oe) ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port a or b pin data out address a[ 7:0] ai06605
133/176 m psd323x port c functionality and structure port c can be configured to perform one or more of the following functions (see figure 66): n mcu i/o mode n cpld output mcellbc7-mcellbc0 outputs can be connected to port b or port c. n cpld input via the input macrocells (imc) n in-system programming (isp) jtag pins (tms, tck, tdi, tdo) are dedicated pins for device programming. (see the section entitled aprogramming in-circuit using the jtag serial interface,o page 142, for more information on jtag programming.) n open drain port c pins can be configured in open drain mode n battery backup features pc2 can be configured for a battery input supply, voltage stand-by (v stby ). pc4 can be configured as a battery-on indicator (v baton ), indicating when v cc is less than v bat . port c does not support address out mode, and therefore no control register is required. figure 66. port c structure note: 1. isp or battery back-up mcu data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term (.oe) read mux p d b cpld-input dir reg. input macrocell enable out special function 1 special function 1 configuration bit data in output select output mux port c pin data out ai06618
m psd323x 134/176 port d functionality and structure port d has two i/o pins (only one pin, pd1, in the 52-pin package). see figure 67 and figure 68. this port does not support address out mode, and therefore no control register is required. of the eight bits in the port d registers, only bits 2 and 1 are used to configure pins pd2 and pd1. port d can be configured to perform one or more of the following functions: n mcu i/o mode n cpld output external chip select (ecs1- ecs2) n cpld input direct input to the cpld, no input macrocells (imc) n slew rate pins can be set up for fast slew rate port d pins can be configured in psdsoft express as input pins for other dedicated functions: n clkin (pd1) as input to the macrocells flip- flops and apd counter n psd chip select input (csi, pd2). driving this signal high disables the flash memory, sram and csiop. figure 67. port d structure mcu data bus data out reg. dq dq wr wr ecs [ 2:1] read mux p d b cpld -input dir reg. data in enable product term (.oe) output select output mux port d pin data out ai06606
135/176 m psd323x external chip select the cpld also provides two external chip select (ecs1-ecs2) outputs on port d pins that can be used to select external devices. each external chip select (ecs1-ecs2) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 68.) figure 68. port d external chip select signals pld input bus polarity bit pd2 pin pt2 ecs2 direction register enable (.oe) polarity bit pd1 pin pt1 ecs1 enable (.oe) direction register cpld and array ai06607
m psd323x 136/176 power management all psd module offers configurable power sav- ing options. these options may be used individu- ally or in combinations, as follows: n the primary and secondary flash memory, and sram blocks are built with power management technology. in addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory awakes up,o changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingeit happens automatically. the pld sections can also achieve standby mode when its inputs are not changing, as de- scribed in the sections on the power manage- ment mode registers (pmmr). n as with the power management mode, the automatic power down (apd) block allows the psd module to reduce to stand-by current automatically. the apd unit can also block mcu address/data signals from reaching the memories and plds. the apd unit is described in more detail in the sections entitled athe psd module has a turbo bit in pmmr0. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc current component and the ac component is higher...,o page 137. built in logic monitors the address strobe of the mcu for activity. if there is no activity for a cer- tain time period (mcu is asleep), the apd unit initiates power-down mode (if enabled). once in power-down mode, all address/data signals are blocked from reaching memory and plds, and the memories are deselected internally. this al- lows the memory and plds to remain in standby mode even if the address/data signals are changing state externally (noise, other de- vices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of stand-by mode, but not the memories. n psd chip select input (csi, pd2) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd unit. there is a slight penalty in memory access time when psd chip select input (csi, pd2) makes its initial transition from deselected to selected. n the pmmrs can be written by the mcu at run- time to manage power. the psd module supports ablocking bitso in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 72 and figure 73). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. figure 69. apd unit apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface csiop select flash select sram select pd clr pd disable flash/sram pld select ai06608
137/176 m psd323x the psd module has a turbo bit in pmmr0. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc cur- rent). even when inputs do change, significant power can be saved at lower frequencies (ac cur- rent), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc cur- rent component and the ac component is higher. automatic power-down (apd) unit and power- down mode. the apd unit, shown in figure 69, puts the psd module into power-down mode by monitoring the activity of address strobe (ale). if the apd unit is enabled, as soon as activity on ad- dress strobe (ale) stops, a four-bit counter starts counting. if address strobe (ale/as, pd0) re- mains inactive for fifteen clock periods of clkin (pd1), power-down (pdn) goes high, and the psd module enters power-down mode, as dis- cussed next. power-down mode. by default, if you enable the apd unit, power-down mode is automatically en- abled. the device enters power-down mode if ad- dress strobe (ale) remains inactive for fifteen periods of clkin (pd1). the following should be kept in mind when the psd module is in power-down mode: n if address strobe (ale) starts pulsing again, the psd module returns to normal operating mode. the psd module also returns to normal operating mode if either psd chip select input (csi, pd2) is low or the reset input is high. n the mcu address/data bus is blocked from all memory and plds. n various signals can be blocked (prior to power- down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clkin (pd1). note: blocking clkin (pd1) from the plds does not block clkin (pd1) from the apd unit. n all memories enter standby mode and are drawing standby current. however, the pld and i/o ports blocks do not go into standby mode because you don't want to have to wait for the logic and i/o to awake-upo before their outputs can change. see table 101 for power-down mode effects on psd module ports. n typical standby current is of the order of microamperes. these standby current values assume that there are no transitions on any pld input. other power saving options. the psd mod- ule offers other reduced power saving options that are independent of the power-down mode. except for the sram stand-by and psd chip se- lect input (csi, pd2) features, they are enabled by setting bits in pmmr0 and pmmr2. figure 70. enable power-down flow chart table 101. power-down mode's effect on ports port function pin level mcu i/o no change pld out no change address out undefined peripheral i/o tri-state enable apd set pmmr0 bit 1 = 1 psd module in power down mode ale idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 2 through 6. ai06609
m psd323x 138/176 pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in pmmr0. by setting the bit to '1,' the turbo mode is off and the plds con- sume the specified stand-by current when the in- puts are not switching for an extended time of 70ns. the propagation delay time is increased by 10ns (for a 5v device) after the turbo bit is set to '1' (turned off) when the inputs change at a com- posite frequency of less than 15mhz. when the turbo bit is reset to '0' (turned on), the plds run at full power and speed. the turbo bit affects the pld's dc power, ac power, and propagation de- lay. when the turbo mode is off, the m psd3200 input clock frequency is reduced by 5mhz from the maximum rated clock frequency. blocking mcu control signals with the bits of pmmr2 can further reduce pld ac power con- sumption. sram standby mode (battery backup). the sram in the psd module supports a battery backup mode in which the contents are retained in the event of a power loss. the sram has voltage stand-by (v stby , pc2) that can be connected to an external battery. when v cc becomes lower than v stby then the sram automatically con- nects to voltage stand-by (v stby , pc2) as a pow- er source. the sram standby current (i stby )is typically 0.5 m a. the sram data retention voltage is 2v minimum. the battery-on indicator (v baton ) can be routed to pc4. this signal indi- cates when the v cc has dropped below v stby . psd chip select input (csi, pd2) pd2 of port d can be configured in psdsoft ex- press as psd chip select input (csi). when low, the signal selects and enables the psd module flash memory, sram, and i/o blocks for read or write operations. a high on psd chip select in- put (csi, pd2) disables the flash memory, and sram, and reduces power consumption. howev- er, the pld and i/o signals remain operational when psd chip select input (csi, pd2) is high. input clock clkin (pd1) can be turned off, to the pld to save ac power consumption. clkin (pd1) is an input to the pld and array and the output macrocells (omc). during power-down mode, or, if clkin (pd1) is not being used as part of the pld logic equation, the clock should be disabled to save ac power. clkin (pd1) is disconnected from the pld and array or the macrocells block by setting bits 4 or 5 to a '1' in pmmr0. input control signals the psd module provides the option to turn off the mcu signals (wr, rd, psen, and address strobe (ale)) to the pld to save ac power con- sumption. these control signals are inputs to the pld and array. during power-down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be dis- abled to save ac power. they are disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a '1' in pmmr2. table 102. power management mode registers pmmr0 1 bit 0 x 0 not used, and should be set to zero. bit 1 apd enable 0 = off automatic power-down (apd) is disabled. 1 = on automatic power-down (apd) is enabled. bit 2 x 0 not used, and should be set to zero. bit 3 pld turbo 0 = on pld turbo mode is on 1 = off pld turbo mode is off, saving power. m psd3200 operates at 5mhz below the maximum rated clock frequency bit 4 pld array clk 0=on clkin (pd1) input to the pld and array is connected. every change of clkin (pd1) powers-up the pld when turbo bit is '0.' 1 = off clkin (pd1) input to pld and array is disconnected, saving power. bit 5 pld mcell clk 0 = on clkin (pd1) input to the pld macrocells is connected. 1 = off clkin (pd1) input to pld macrocells is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero.
139/176 m psd323x table 103. power management mode registers pmmr2 1 note: 1. the bits of this register are cleared to zero following power-up. subsequent reset pulses do not clear the registers. table 104. apd counter operation bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 pld array wr 0 = on wr input to the pld and array is connected. 1 = off wr input to pld and array is disconnected, saving power. bit 3 pld array rd 0 = on rd input to the pld and array is connected. 1 = off rd input to pld and array is disconnected, saving power. bit 4 pld array psen 0 = on psen input to the pld and array is connected. 1 = off psen input to pld and array is disconnected, saving power. bit 5 pld array ale 0 = on ale input to the pld and array is connected. 1 = off ale input to pld and array is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero. apd enable bit ale level apd counter 0 x not counting 1 pulsing not counting 1 0 or 1 counting (generates pdn after 15 clocks)
m psd323x 140/176 reset timing and device status at reset upon power-up, the psd module requires a re- set (reset) pulse of duration t nlnh-po after v cc is steady. during this period, the device loads in- ternal configurations, clears some of the registers and sets the flash memory into operating mode. after the rising edge of reset (reset), the psd module remains in the reset mode for an addi- tional period, t opr , before the first memory access is allowed. the flash memory is reset to the read mode upon power-up. sector select (fs0-fs7 and csboot0-csboot3) must all be low, write strobe (wr, cntl0) high, during power-on reset for maximum security of the data contents and to remove the possibility of a byte being writ- ten on the first edge of write strobe (wr). any flash memory write cycle initiation is prevented automatically when v cc is below v lko . warm reset once the device is up and running, the psd mod- ule can be reset with a pulse of a much shorter duration, t nlnh . the same t opr period is needed before the device is operational after a warm reset. figure 71 shows the timing of the power- up and warm reset. i/o pin, register and pld status at reset table 105 shows the i/o pin, register and pld sta- tus during power-on reset, warm reset, and power-down mode. pld outputs are always valid during warm reset, and they are valid in power- on reset once the internal configuration bits are loaded. this loading is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are de- termined by the pld equations. reset of flash memory erase and program cycles a reset (reset) also resets the internal flash memory state machine. during a flash memory program or erase cycle, reset (reset) termi- nates the cycle and returns the flash memory to the read mode within a period of t nlnh-a . figure 71. reset (reset) timing t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
141/176 m psd323x table 105. status during power-on reset, warm reset and power-down mode note: 1. the sr_cod and periphmode bits in the vm register are always cleared to '0' on power-on reset or warm reset. port config uration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined peripheral i/o tri-stated tri-stated tri-stated register power-on reset warm reset power-down mode pmmr0 and pmmr2 cleared to '0' unchanged unchanged macrocells flip-flop status cleared to '0' by internal power-on reset depends on .re and .pr equations depends on .re and .pr equations vm register 1 initialized, based on the selection in psdsoft configuration menu initialized, based on the selection in psdsoft configuration menu unchanged all other registers cleared to '0' cleared to '0' unchanged
m psd323x 142/176 programming in-circuit using the jtag serial interface the jtag serial interface pins (tms, tck, tdi, tdo) are dedicated pins on port c (see table 106). all memory blocks (primary and secondary flash memory), pld logic, and psd module configuration register bits may be programmed through the jtag serial interface block. a blank device can be mounted on a printed circuit board and programmed using jtag. the standard jtag signals (ieee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr, are optional jtag extensions used to speed up program and erase cycles. by default, on a blank device (as shipped from the factory or after erasure), four pins on port c are the basic jtag signals tms, tck, tdi, and tdo . standard jtag signals at power-up, the standard jtag pins are inputs, waiting for a jtag serial command from an exter- nal jtag controller device (such as flashlink or automated test equipment). when the enabling command is received, tdo becomes an output and the jtag channel is fully functional. the same command that enables the jtag channel may optionally enable the two additional jtag sig- nals, tstat and terr. the reset input to the m ps3200 should be active during jtag programming. the active reset puts the mcu module into reset mode while the psd module is being programmed. see applica- tion note an1153 for more details on jtag in- system programming (isp). the m psd323x devices supports jtag in-sys- tem-configuration (isc) commands, but not boundary scan. the psdsoft express software tool and flashlink jtag programming cable im- plement the jtag in-system-configuration (isc) commands. a definition of these jtag in-system- configuration (isc) commands and sequences is defined in a supplemental document available from st. this document is needed only as a refer- ence for designers who use a flashlink to pro- gram the m psd323x devices. table 106. jtag port signals jtag extensions tstat and terr are two jtag extension signals enabled by an aisc_enableo command received over the four standard jtag signals (tms, tck, tdi, and tdo). they are used to speed program and erase cycles by indicating status on m pds signals instead of having to scan the status out se- rially using the standard jtag channel. see appli- cation note an1153 . terr indicates if an error has occurred when erasing a sector or programming a byte in flash memory. this signal goes low (active) when an error condition occurs, and stays low until an aisc_clearo command is executed or a chip re- set (reset) pulse is received after an aisc_disableo command. tstat behaves the same as ready/busy de- scribed in the section entitled aready/busy (pc3),o page 107. tstat is high when the psd module device is in read mode (primary and secondary flash memory contents can be read). tstat is low when flash memory program or erase cycles are in progress, and also when data is being writ- ten to the secondary flash memory. tstat and terr can be configured as open- drain type signals during an aisc_enableo com- mand. security and flash memory protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program, erase and verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft express configuration. all primary and secondary flash memory sectors can individually be sector protected against era- sures. the sector protect bits can be set in psd- soft express configuration. initial delivery state when delivered from st, the m psd323x devices have all bits in the memory and plds set to '1.' the code, configuration, and pld logic are loaded using the programming procedure. information for programming the device is available directly from st. please contact your local sales representa- tive. port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status (optional) pc4 terr error flag (optional) pc5 tdi serial data in pc6 tdo serial data out
143/176 m psd323x ac/dc parameters these tables describe the ad and dc parameters of the m psd323x devices: dc electrical specification ac timing specification n pld timing combinatorial timing synchronous clock mode asynchronous clock mode input macrocell timing n mcu module timing read timing write timing power-down and reset timing the following are issues concerning the parame- ters presented: n in the dc specification the supply current is given for different modes of operation. n the ac power component gives the pld, flash memory, and sram ma/mhz specification. figure 72 and figure 73 show the pld ma/mhz as a function of the number of product terms (pt) used. n in the pld timing parameters, add the required delay when turbo bit is '0.' figure 72. pld i cc /frequency consumption (5v range) figure 73. pld i cc /frequency consumption (3v range) 0 10 20 30 40 60 70 80 90 100 110 v cc =5v 50 01015 52025 highest composite frequency at pld inputs (mhz) i cc (ma) turbo on (100%) turbo on (25%) turbo off turbo off pt 100% pt 25% ai02894 0 10 20 30 40 50 60 v cc =3v 01015 52025 i cc (ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100
m psd323x 144/176 table 107. psd module example, typ. power calculation at v cc = 5.0v (turbo mode off) conditions mcu clock frequency = 12mhz highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 2mhz % flash memory access =80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 40% % power-down mode = 60% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = off calculation (using typical values) i cc total = i cc (mcuactive) x %mcuactive + i cc (psdactive) x %psdactive + i pd (pwrdown) x %pwrdown i cc (mcuactive) =20ma i pd (pwrdown) = 250 m a i cc (psdactive) = i cc (ac) + i cc (dc) = %flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld) = 0.8 x 2.5 ma/mhz x 2mhz + 0.15 x 1.5 ma/mhz x 2mhz + 24 ma = (4 + 0.45 + 24) ma = 28.45ma i cc total = 20ma x 40% + 28.45ma x 40% + 250 m a x 60% = 8ma + 11.38ma + 150 m a = 19.53ma this is the operating power with no flash memory erase or program cycles in progress. calculation is based on all i/o pins being disconnected and i out = 0 ma.
145/176 m psd323x maximum rating stressing the device above the rating listed in the absolute maximum ratingso table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 108. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature 65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) 0.5 6.5 v v cc supply voltage 0.5 6.5 v v pp device programmer supply voltage 0.5 14.0 v v esd electrostatic discharge voltage (human body model) 2 2000 2000 v
m psd323x 146/176 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 109. operating conditions (5v devices) table 110. operating conditions (3v devices) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (industrial) 40 85 c ambient operating temperature (commercial) 0 70 c symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (industrial) 40 85 c ambient operating temperature (commercial) 0 70 c
147/176 m psd323x table 111. ac symbols for timing example: t avlx time from address valid to ale invalid. figure 74. switching waveforms key signal letters signal behavior a address t time c clock l logic level low or ale d input data h logic level high i instruction v valid l ale x no longer a valid logic level n reset input or output z float p psen signal pw pulse width q output data r rd signal w wr signal b v stby output m output macrocell waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
m psd323x 148/176 table 112. dc characteristics (5v devices) symbol parameter test conditi on (in addition to those in table 109, page 146) min. typ. max. unit v ih input high voltage (ports 1, 2, 3, 4[bits 7,6,5,4,3,1,0], xtal1, reset) 4.5v < v cc < 5.5v 0.7v cc v cc + 0.5 v v ih1 input high voltage (ports a, b, c, d, 4[bit 2], usb+, usb) 4.5v < v cc < 5.5v 2.0 v cc + 0.5 v v il input low voltage (ports 1, 2, 3, 4[bits 7,6,5,4,3,1,0], xtal1, reset) 4.5v < v cc < 5.5v v ss 0.5 0.3v cc v v il1 input low voltage (ports a, b, c, d, 4[bit 2]) 4.5v < v cc < 5.5v 0.5 0.8 v input high voltage (usb+, usb) 4.5v < v cc < 5.5v v ss 0.5 0.8 v v ol output low voltage (ports a,b,c,d) i ol =20 m a v cc = 4.5v 0.01 0.1 v i ol = 8ma v cc = 4.5v 0.25 0.45 v v ol1 output low voltage (ports 1,2,3,4, wr, rd) i ol = 1.6ma 0.45 v v ol2 output low voltage (port 0, ale, psen) i ol = 3.2ma 0.45 v v oh output high voltage (ports a,b,c,d) i oh = 20 m a v cc = 4.5v 4.4 4.49 v i oh = 2ma v cc = 4.5v 2.4 3.9 v v oh1 output high voltage (ports 1,2,3,4, wr, rd) i oh = 80 m a 2.4 v i oh = 10 m a 4.05 v v oh2 output high voltage (port 0 in ext. bus mode, ale, psen)) 4 i oh = 800 m a 2.4 v i oh = 80 m a 4.05 v v oh3 output high voltage v stbyon i oh =1 m av stby 0.8 v v lvr low voltage reset 0.1v hysteresis 3.75 4.0 4.25 v v op xtal open bias voltage (xtal1, xtal2) i ol = 3.2ma 2.0 3.0 v v lko v cc (min) for flash erase and program 2.5 4.2 v v stby sram (psd) stand-by voltage 2.0 v cc v v df sram (psd) data retention voltage only on v stby 2v i il logic '0' input current (ports 1,2,3,4) v in = 0.45v (0v for port 4[pin 2]) 10 50 m a i tl logic 1-to-0 transition current (ports 1,2,3,4) v in = 3.5v (2.5v for port 4[pin 2]) 65 650 m a
149/176 m psd323x note: 1. i pd (power-down mode) is measured with: xtal1=v ss ; xtal2=not connected; reset=v cc ; port 0 =v cc ; all other pins are disconnected. pld not in turbo mode. 2. i cc_cpu (active mode) is measured with: xtal1 driven with t clch ,t chcl = 5ns, v il =v ss +0.5v, v ih = vcc 0.5v, xtal2 = not connected; reset=v ss ; port 0=v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (approximately 1ma). 3. i cc_cpu (idle mode) is measured with: xtal1 driven with t clch ,t chcl = 5ns, v il =v ss +0.5v, v ih =v cc 0.5v, xtal2 = not connected; port 0 = v cc ; reset=v cc ; all other pins are disconnected. 4. pld is in non-turbo mode and none of the inputs are switching. 5. see figure 72 for the pld current calculation. 6. i/o current = 0 ma, all i/o pins are disconnected. i stby sram (psd) stand-by current (v stby input) v cc =0v 0.5 1 m a i idle sram (psd) idle current (v stby input) v cc >v stby 0.1 0.1 m a i rst reset pin pull-up current (reset) v in =v ss 10 55 m a i fr xtal feedback resistor current (xtal1) xtal1 = v cc xtal2 = v ss 20 50 m a i li input leakage current v ss m psd323x 150/176 table 113. dc characteristics (3v devices) symbol parameter test condition (in additio n to those in table 110, page 146) min. typ. max. unit v ih input high voltage (ports 1, 2, 3, 4[bits 7,6,5,4,3,1,0], a, b, c, d, xtal1, reset) 3.0v < v cc < 3.6v 0.7v cc v cc + 0.5 v v ih1 input high voltage (port 4[bit 2]) 3.0v < v cc < 3.6v 2.0 v cc + 0.5 v v il input high voltage (ports 1, 2, 3, 4[bits 7,6,5,4,3,1,0], xtal1, reset) 3.0v < v cc < 3.6v v ss 0.5 0.3v cc v v il1 input low voltage (ports a, b, c, d) 3.0v < v cc < 3.6v 0.5 0.8 v input low voltage (port 4[bit 2]) 3.0v < v cc < 3.6v v ss 0.5 0.8 v v ol output low voltage (ports a,b,c,d) i ol =20 m a v cc = 3.0v 0.01 0.1 v i ol = 4ma v cc = 3.0v 0.15 0.45 v v ol1 output low voltage (ports 1,2,3,4, wr, rd) i ol = 1.6ma 0.45 v i ol = 100 m a 0.3 v v ol2 output low voltage (port 0, ale, psen) i ol = 3.2ma 0.45 v i ol = 200 m a 0.3 v v oh output high voltage (ports a,b,c,d) i oh = 20 m a v cc = 3.0v 2.9 2.99 v i oh = 1ma v cc = 3.0v 2.4 2.6 v v oh1 output high voltage (ports 1,2,3,4, wr, rd) i oh = 20 m a 2.0 v i oh = 10 m a 2.7 v v oh2 output high voltage (port 0 in ext. bus mode, ale, psen)) 4 i oh = 800 m a 2.0 v i oh = 80 m a 2.7 v v oh3 output high voltage v stbyon i oh =1 m av stby 0.8 v v lvr low voltage reset 0.1v hysteresis 2.3 2.5 2.7 v v op xtal open bias voltage (xtal1, xtal2) i ol = 3.2ma 1.0 2.0 v v lko v cc (min) for flash erase and program 1.5 2.2 v v stby sram (psd) stand-by voltage 2.0 v cc v v df sram (psd) data retention voltage only on v stby 2v i il logic '0' input current (ports 1,2,3,4) v in = 0.45v (0v for port 4[pin 2]) 1 50 m a
151/176 m psd323x note: 1. i pd (power-down mode) is measured with: xtal1=v ss ; xtal2=not connected; reset=v cc ; port 0 =v cc ; all other pins are disconnected. pld not in turbo mode. 2. i cc_cpu (active mode) is measured with: xtal1 driven with t clch ,t chcl = 5ns, v il =v ss +0.5v, v ih = vcc 0.5v, xtal2 = not connected; reset=v ss ; port 0=v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (approximately 1ma). 3. i cc_cpu (idle mode) is measured with: xtal1 driven with t clch ,t chcl = 5ns, v il =v ss +0.5v, v ih =v cc 0.5v, xtal2 = not connected; port 0 = v cc ; reset=v cc ; all other pins are disconnected. 4. pld is in non-turbo mode and none of the inputs are switching. 5. see figure 72 for the pld current calculation. 6. i/o current = 0 ma, all i/o pins are disconnected. i tl logic 1-to-0 transition current (ports 1,2,3,4) v in = 3.5v (2.5v for port 4[pin 2]) 25 250 m a i stby sram (psd) stand-by current (v stby input) v cc = 0v 0.5 1 m a i idle sram (psd) idle current (v stby input) v cc >v stby 0.1 0.1 m a i rst reset pin pull-up current (reset) v in =v ss 10 55 m a i fr xtal feedback resistor current (xtal1) xtal1 = v cc xtal2 = v ss 20 50 m a i li input leakage current v ss m psd323x 152/176 figure 75. external program memory read cycle table 114. external program memory ac characteristics (with the 5v mcu module) note: 1. conditions (in addition to those in table 109, v cc = 4.5 to 5.5v): v ss = 0v; c l for port 0, ale and psen output is 100pf; c l for other outputs is 80pf 2. interfacing the m psd323x devices to devices with float times up to 20ns is permissible. this limit ed bus contention does not cause any damage to port 0 drivers. symbol parameter 1 40mhz oscillator variable oscillator 1/t clcl = 24 to 40mhz unit min max min max t lhll ale pulse width 35 2t clcl 15 ns t avll address set-up to ale 10 t clcl 15 ns t llax address hold after ale 10 t clcl 15 ns t lliv ale low to valid instruction in 55 4t clcl 45 ns t llpl ale to psen 10 t clcl 15 ns t plph psen pulse width 60 3t clcl 15 ns t pliv psen to valid instruction in 30 3t clcl 45 ns t pxix input instruction hold after psen 0 0 ns t pxiz 2 input instruction float after psen 15 t clcl 10 ns t pxav 2 address valid after psen 20 t clcl 5 ns t aviv address to valid instruction in 70 5t clcl 55 ns t azpl address float to psen 5 5 ns t avll t plph t pxiz t aviv psen port 2 port 0 ai06848 t lhll ale t llpl a0-a7 t llax t azpl t lliv t pliv a0-a7 t pxav t pxix a8-a11 instr in a8-a11
153/176 m psd323x table 115. external program memory ac characteristics (with the 3v mcu module) note: 1. conditions (in addition to those in table 110, v cc = 3.0 to 3.6v): v ss = 0v; c l for port 0, ale and psen output is 100pf, for 5v devices, and 50pf for 3v devices; c l for other outputs is 80pf, for 5v devices, and 50pf for 3v devices) 2. interfacing the m psd323x devices to devices with float times up to 35ns is permissible. this limit ed bus contention does not cause any damage to port 0 drivers. table 116. external clock drive (with the 5v mcu module) note: 1. conditions (in addition to those in table 109, v cc = 4.5 to 5.5v): v ss = 0v; c l for port 0, ale and psen output is 100pf; c l for other outputs is 80pf table 117. external clock drive (with the 3v mcu module) note: 1. conditions (in addition to those in table 110, v cc = 3.0 to 3.6v): v ss = 0v; c l for port 0, ale and psen output is 100pf, for 5v devices, and 50pf for 3v devices; c l for other outputs is 80pf, for 5v devices, and 50pf for 3v devices) symbol parameter 1 24mhz oscillator variable oscillator 1/t clcl = 8 to 24mhz unit min max min max t lhll ale pulse width 43 2t clcl 40 ns t avll address set-up to ale 17 t clcl 25 ns t llax address hold after ale 17 t clcl 25 ns t lliv ale low to valid instruction in 80 4t clcl 87 ns t llpl ale to psen 22 t clcl 20 ns t plph psen pulse width 95 3t clcl 30 ns t pliv psen to valid instruction in 60 3t clcl 65 ns t pxix input instruction hold after psen 0 0 ns t pxiz 2 input instruction float after psen 32 t clcl 10 ns t pxav 2 address valid after psen 37 t clcl 5 ns t aviv address to valid instruction in 148 5t clcl 60 ns t azpl address float to psen 10 10 ns symbol parameter 1 40mhz oscillator variable oscillator 1/t clcl = 24 to 40mhz unit min max min max t rlrh oscillator period 25 41.7 ns t wlwh high time 10 t clcl t clcx ns t llax2 low time 10 t clcl t clcx ns t rhdx rise time 10 ns t rhdx fall time 10 ns symbol parameter 1 24mhz oscillator variable oscillator 1/t clcl = 8 to 24mhz unit min max min max t rlrh oscillator period 41.7 125 ns t wlwh high time 12 t clcl t clcx ns t llax2 low time 12 t clcl t clcx ns t rhdx rise time 12 ns t rhdx fall time 12 ns
m psd323x 154/176 figure 76. external data memory read cycle figure 77. external data memory write cycle port 2 port 0 ale rd psen p2.0 to p2.3 or a8-a11 from dph a8-a11 from pch tavdv trldv tllwl trlrh tavll tlldv tlhll trlaz data in a0-a7 from pcl instr in a0-a7 from ri or dpl tllax2 tavwl trhdz twhlh ai07088 trhdx port 2 port 0 ale wr psen p2.0 to p2.3 or a8-a11 from dph a8-a11 from pch tqvwx tllwl twlwh tavll tlhll tqvwh data out a0-a7 from pcl instr in a0-a7 from ri or dpl tllax tavwl twhqx twhlh ai07089
155/176 m psd323x table 118. external data memory ac characteristics (with the 5v mcu module) note: 1. conditions (in addition to those in table 109, v cc = 4.5 to 5.5v): v ss = 0v; c l for port 0, ale and psen output is 100pf; c l for other outputs is 80pf symbol parameter 1 40mhz oscillator variable oscillator 1/t clcl = 24 to 40mhz unit min max min max t rlrh rd pulse width 120 6t clcl 30 ns t wlwh wr pulse width 120 6t clcl 30 ns t llax2 address hold after ale 10 t clcl 15 ns t rhdx rd to valid data in 75 5t clcl 50 ns t rhdx data hold after rd 0 0 ns t rhdz data float after rd 38 2t clcl 12 ns t lldv ale to valid data in 150 8t clcl 50 ns t avdv address to valid data in 150 9t clcl 75 ns t llwl ale to wr or rd 60 90 3t clcl 15 t clcl +15 ns t avwl address valid to wr or rd 70 4t clcl 30 ns t whlh wr or rd high to ale high 10 40 t clcl 15 t clcl +15 ns t qvwx data valid to wr transition 5 t clcl 20 ns t qvwh data set-up before wr 125 7t clcl 50 ns t whqx data hold after wr 5 t clcl 20 ns t rlaz address float after rd 0 0 ns
m psd323x 156/176 table 119. external data memory ac characteristics (with the 3v mcu module) note: 1. conditions (in addition to those in table 110, v cc = 3.0 to 3.6v): v ss = 0v; c l for port 0, ale and psen output is 100pf, for 5v devices, and 50pf for 3v devices; c l for other outputs is 80pf, for 5v devices, and 50pf for 3v devices) table 120. a/d analog specification symbol parameter 1 24mhz oscillator variable oscillator 1/t clcl = 8 to 24mhz unit min max min max t rlrh rd pulse width 180 6t clcl 70 ns t wlwh wr pulse width 180 6t clcl 70 ns t llax2 address hold after ale 56 2t clcl 27 ns t rhdx rd to valid data in 118 5t clcl 90 ns t rhdx data hold after rd 0 0 ns t rhdz data float after rd 63 2t clcl 20 ns t lldv ale to valid data in 200 8t clcl 133 ns t avdv address to valid data in 220 9t clcl 155 ns t llwl ale to wr or rd 75 175 3t clcl 50 t clcl +50 ns t avwl address valid to wr or rd 67 4t clcl 97 ns t whlh wr or rd high to ale high 17 67 t clcl 25 t clcl +25 ns t qvwx data valid to wr transition 5 t clcl 37 ns t qvwh data set-up before wr 170 7t clcl 122 ns t whqx data hold after wr 15 t clcl 27 ns t rlaz address float after rd 0 0 ns symbol parameter test condition min. typ. max. unit av ref analog power supply input voltage range v ss v cc v v an analog input voltage range v ss 0.3 av ref + 0.3 v i avdd current following between v cc and v ss 200 m a ca in overall accuracy 2 l.s.b. n nle non-linearity error 2 l.s.b. n dnle differential non-linearity error 2 l.s.b. n zoe zero-offset error 2 l.s.b. n fse full scale error 2 l.s.b. n ge gain error 2 l.s.b. t conv conversion time at 8mhz clock 20 m s
157/176 m psd323x figure 78. input to output disable / enable table 121. cpld combinatorial timing (5v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd1. decrement times by given amount 2. t pd for mcu address and control signals refers to delay from pins on port 0, port 2, rd wr, psen and ale to cpld combinatorial output (80-pin package only) table 122. cpld combinatorial timing (3v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd1. decrement times by given amount 2. t pd for mcu address and control signals refers to delay from pins on port 0, port 2, rd wr, psen and ale to cpld combinatorial output (80-pin package only) symbol parameter conditions min max pt aloc turbo off slew rate 1 unit t pd 2 cpld input pin/feedback to cpld combinatorial output 20 + 2 + 10 2 ns t ea cpld input to cpld output enable 21 + 10 2 ns t er cpld input to cpld output disable 21 + 10 2 ns t arp cpld register clear or preset delay 21 + 10 2 ns t arpw cpld register clear or preset pulse width 10 + 10 ns t ard cpld array delay any macrocell 11 + 2 ns symbol parameter conditions min max pt aloc turbo off slew rate 1 unit t pd 2 cpld input pin/feedback to cpld combinatorial output 40 + 4 + 20 6 ns t ea cpld input to cpld output enable 43 + 20 6 ns t er cpld input to cpld output disable 43 + 20 6 ns t arp cpld register clear or preset delay 40 + 20 6 ns t arpw cpld register clear or preset pulse width 25 + 20 ns t ard cpld array delay any macrocell 25 + 4 ns ter tea input input to output enable/disable ai02863
m psd323x 158/176 figure 79. synchronous clock mode timing pld table 123. cpld macrocell synchronous clock mode timing (5v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd1. decrement times by given amount. 2. clkin (pd1) t clcl =t ch +t cl . symbol parameter conditio ns min max pt aloc turbo off slew rate 1 unit f max maximum frequency external feedback 1/(t s +t co ) 40.0 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co 10) 66.6 mhz maximum frequency pipelined data 1/(t ch +t cl ) 83.3 mhz t s input setup time 12 + 2 + 10 ns t h input hold time 0 ns t ch clock high time clock input 6 ns t cl clock low time clock input 6 ns t co clock to output delay clock input 13 2 ns t ard cpld array delay any macrocell 11 + 2 ns t min minimum clock period 2 t ch +t cl 12 ns t ch t cl t co t h t s clkin input registered output ai02860
159/176 m psd323x table 124. cpld macrocell synchronous clock mode timing (3v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd1. decrement times by given amount. 2. clkin (pd1) t clcl =t ch +t cl . symbol parameter conditi ons min max pt aloc turbo off slew rate 1 unit f max maximum frequency external feedback 1/(t s +t co ) 22.2 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co 10) 28.5 mhz maximum frequency pipelined data 1/(t ch +t cl ) 40.0 mhz t s input setup time 20 + 4 + 20 ns t h input hold time 0 ns t ch clock high time clock input 15 ns t cl clock low time clock input 10 ns t co clock to output delay clock input 25 6 ns t ard cpld array delay any macrocell 25 + 4 ns t min minimum clock period 2 t ch +t cl 25 ns
m psd323x 160/176 figure 80. asynchronous reset / preset figure 81. asynchronous clock mode timing (product term clock) table 125. cpld macrocell asynchronous clock mode timing (5v devices) symbol parameter conditi ons min max pt aloc turbo off slew rate unit f maxa maximum frequency external feedback 1/(t sa +t coa ) 38.4 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa 10) 62.5 mhz maximum frequency pipelined data 1/(t cha +t cla ) 71.4 mhz t sa input setup time 7 + 2 + 10 ns t ha input hold time 8 ns t cha clock input high time 9 + 10 ns t cla clock input low time 9 + 10 ns t coa clock to output delay 21 + 10 2 ns t arda cpld array delay any macrocell 11 + 2 ns t mina minimum clock period 1/f cnta 16 ns tarp register output tarpw reset/preset input ai02864 tcha tcla tcoa tha tsa clock input registered output ai02859
161/176 m psd323x table 126. cpld macrocell asynchronous clock mode timing (3v devices) symbol parameter conditi ons min max pt aloc turbo off slew rate unit f maxa maximum frequency external feedback 1/(t sa +t coa ) 21.7 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa 10) 27.8 mhz maximum frequency pipelined data 1/(t cha +t cla ) 33.3 mhz t sa input setup time 10 + 4 + 20 ns t ha input hold time 12 ns t cha clock high time 17 + 20 ns t cla clock low time 13 + 20 ns t coa clock to output delay 36 + 20 6 ns t ard cpld array delay any macrocell 25 + 4 ns t mina minimum clock period 1/f cnta 36 ns
m psd323x 162/176 figure 82. input macrocell timing (product term clock) table 127. input macrocell timing (5v devices) note: 1. inputs from port a, b, and c relative to register/ latch clock from the pld. ale/as latch timings refer to t avlx and t lxax . table 128. input macrocell timing (3v devices) note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . symbol parameter condition s min max pt aloc turbo off unit t is input setup time (note 1 ) 0ns t ih input hold time (note 1 ) 15 + 10 ns t inh nib input high time (note 1 ) 9ns t inl nib input low time (note 1 ) 9ns t ino nib input to combinatorial delay (note 1 ) 34 +2 +10 ns symbol parameter condition s min max pt aloc turbo off unit t is input setup time (note 1 ) 0ns t ih input hold time (note 1 ) 25 + 20 ns t inh nib input high time (note 1 ) 12 ns t inl nib input low time (note 1 ) 12 ns t ino nib input to combinatorial delay (note 1 ) 46 +4 +20 ns t inh t inl t ino t ih t is pt clock input output ai03101
163/176 m psd323x table 129. program, write and erase times (5v devices) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid t q7vqv time units before the data byte, dq0-dq7, is valid for reading. table 130. program, write and erase times (3v devices) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid t q7vqv time units before the data byte, dq0-dq7, is valid for reading. symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 5 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 m s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 m s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 5 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 m s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 m s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns
m psd323x 164/176 figure 83. peripheral i/o read timing table 131. port a peripheral data mode read timing (5v devices) note: 1. any input used to select port a data peripheral mode. 2. data is already stable on port a. table 132. port a peripheral data mode read timing (3v devices) note: 1. any input used to select port a data peripheral mode. 2. data is already stable on port a. symbol parameter conditions min max turbo off unit t avqvpa address valid to data valid (note 1 ) 37 + 10 ns t slqvpa csi valid to data valid 27 + 10 ns t rlqvpa rd to data valid (note 2 ) 32 ns t dvqvpa data in to data out valid 22 ns t rhqzpa rd to data high-z 23 ns symbol parameter conditions min max turbo off unit t avqvpa address valid to data valid (note 1 ) 50 + 20 ns t slqvpa csi valid to data valid 37 + 20 ns t rlqvpa rd to data valid (note 2 ) 45 ns t dvqvpa data in to data out valid 38 ns t rhqzpa rd to data high-z 36 ns t rlqv (pa) t dvqv ( pa) t rhqz (pa) t slqv ( pa) t avqv (pa) address data valid ale a /d bus rd data on port a csi ai06610
165/176 m psd323x figure 84. peripheral i/o write timing table 133. port a peripheral data mode write timing (5v devices) note: 1. data stable on port 0 pins to data on port a. table 134. port a peripheral data mode write timing (3v devices) note: 1. data stable on port 0 pins to data on port a. symbol parameter condit ions min max unit t wlqvpa wr to data propagation delay 25 ns t dvqvpa data to port a data propagation delay (note 1 ) 22 ns t whqzpa wr invalid to port a tri-state 20 ns symbol parameter condit ions min max unit t wlqvpa wr to data propagation delay 42 ns t dvqvpa data to port a data propagation delay (note 1 ) 38 ns t whqzpa wr invalid to port a tri-state 33 ns tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale ai06611
m psd323x 166/176 figure 85. reset (reset) timing table 135. reset (reset) timing (5v devices) note: 1. reset (reset) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. table 136. reset (reset) timing (3v devices) note: 1. reset (reset) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. table 137. v stbyon definitions timing (5v devices) note: 1. v stbyon timing is measured at v cc ramp rate of 2ms. table 138. v stbyon timing (3v devices) note: 1. v stbyon timing is measured at v cc ramp rate of 2ms. symbol parameter conditio ns min max unit t nlnh reset active low time 1 150 ns t nlnhpo power-on reset active low time 1 ms t nlnha warm reset 2 25 m s t opr reset high to operational device 120 ns symbol parameter conditio ns min max unit t nlnh reset active low time 1 300 ns t nlnhpo power-on reset active low time 1 ms t nlnha warm reset 2 25 m s t opr reset high to operational device 300 ns symbol parameter conditio ns min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 20 m s t bxbl v stby off detection to v stbyon output low (note 1 ) 20 m s symbol parameter conditio ns min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 20 m s t bxbl v stby off detection to v stbyon output low (note 1 ) 20 m s t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
167/176 m psd323x figure 86. isc timing table 139. isc timing (5v devices) note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter condit ions min max unit t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 20 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 23 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 23 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 2 mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 ns t iscpsu isc port set up time 7 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 21 ns t iscpzv isc port high-impedance to valid output 21 ns t iscpvz isc port valid output to high-impedance 21 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscp h t iscp su t iscpvz t iscpzv t iscp co t ai02865
m psd323x 168/176 table 140. isc timing (3v devices) note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. figure 87. mcu module ac measurement i/o waveform note: ac inputs during testing are driven at v cc 0.5v for a logic '1,' and 0.45v for a logic '0.' timing measurements are made at v ih (min) for a logic '1,' and v il (max) for a logic '0' figure 88. psd module ac float i/o waveform note: for timing purposes, a port pin is considered to be no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh or v ol level occurs i ol and i oh 20ma symbol parameter condit ions min max unit t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 12 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 40 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 40 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 2 mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 ns t iscpsu isc port set up time 12 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 30 ns t iscpzv isc port high-impedance to valid output 30 ns t iscpvz isc port valid output to high-impedance 30 ns ai06650 v cc 0.5v 0.45v test points 0.2 v cc 0.1v 0.2 v cc + 0.9v ai06651 test reference points v ol + 0.1v v oh 0.1v v load 0.1v v load + 0.1v 0.2 v cc 0.1v
169/176 m psd323x figure 89. external clock cycle figure 90. recommended oscillator circuits note: c1, c2 = 30pf 10pf for crystals for ceramic resonators, contact resonator manufacturer oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. figure 91. psd module ac measurement i/o waveform figure 92. psd moduleac measurement load circuit table 141. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a =25 c and nominal supply voltages. 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 w c l =30 pf (including scope and jig capacitance) ai03104b symbol parameter test condi tion typ. 2 max . unit c in input capacitance (for input pins) v in =0v 46 pf c out output capacitance (for input/ output pins) v out =0v 812 pf
m psd323x 170/176 package mechanical information figure 93. tqfp52 52-lead plastic quad flatpack package outline note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 l1
171/176 m psd323x table 142. tqfp52 52-lead plastic quad flatpack package mechanical data symb mm inches typ min max typ min max a 1.75 0.069 a1 0.05 0.020 0.002 0.008 a2 1.25 1.55 0.049 0.061 b 0.02 0.04 0.007 0.016 c 0.07 0.23 0.002 0.009 d 12.00 0.473 d1 10.00 0.394 d2 e 12.00 0.473 e1 10.00 0.394 e2 e 0.65 0.026 l 0.45 0.75 0.018 0.030 l1 1.00 0.039 a 0 7 0 7 n52 52 nd 13 13 ne 13 13 cp 0.10 0.004
m psd323x 172/176 figure 94. tqfp80 80-lead plastic quad flatpack package outline note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 l1
173/176 m psd323x table 143. tqfp80 80-lead plastic quad flatpack package mechanical data symb mm inches typ min max typ min max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.40 1.35 1.45 0.055 0.053 0.057 b 0.22 0.17 0.27 0.009 0.007 0.011 c 0.09 0.20 0.004 0.008 d 14.00 0.551 d1 12.00 0.472 d2 9.50 0.374 e 14.00 0.473 e1 12.00 0.394 e2 9.50 0.374 e 0.50 0.020 l 0.60 0.45 0.75 0.024 0.018 0.030 l1 1.00 0.039 a 3.5 0 7 3.5 0 7 n80 80 nd 20 20 ne 20 20 cp 0.08 0.003
m psd323x 174/176 part numbering table 144. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact your nearest st sales office. example: m psd3234bv24u6t device type m psd = microcontroller psd family 3 = 8032 core pld size 2 = 16 macrocells sram size 1 = 16kbit 3 = 64kbit main flash memory size 3 = 1mbit 4 = 2mbit ip mix a = usb, i 2 c, pwm, ddc, adc, (2) uarts supervisor (reset out, reset in, lvd, wd) b=i 2 c, pwm, ddc, adc, (2) uarts supervisor (reset out, reset in, lvd, wd) operating voltage blank = v cc = 4.5 to 5.5v v=v cc = 3.0 to 3.6v speed 24 = 24mhz 40 = 40mhz package t = 52-pin tqfp u = 80-pin tqfp temperature range 1=0to70 c 6=40to85 c shipping optio n t = tape and reel packing
175/176 m psd323x revision history table 145. document revision history table 146. device functional change history note: date code is the 6th to the 9th digit of the trace code on top of the device. date rev. # revision details 21-jun-2002 1.0 first issue 18-oct-2002 2.0 document promoted to full datasheet 27-nov-2002 2.1 upsd3200 datasheet split into upsd323x and upsd325x functiona l change after date code 0242 date code 0242 and before pwm block an 8-bit, programmable pwm 4 channel and the associated registers are added. only pwm0-pwm3 channels are available. ddc sram mapping when ddc is disabled, the data space ff00h-ffffh assigned to ddc sram is available for external data mapping. the swenb bit definition in the ddcon register is modified. data space ff00h-ffffh is dedicated to ddc sram. usb reset function 1. option to block usb generated reset from resetting the mcu/psd modules. 2. allow usb reset flag (rstf) to interrupt mcu. 3. add rste and rstfie bits to the uien interrupt enable register. usb-generated reset always resets both, the usb and the mcu/psd modules.
m psd323x 176/176 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - swit zerland - united kingdom - u.s.a. www.st.com

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